Method and system for fabricating fiducials using selective area growth
A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.
1. A method of forming alignment marks, the method comprising:
providing a III-V compound substrate having a device region and an alignment mark region, wherein the III-V compound substrate is characterized by a processing surface;
forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the processing surface of the III-V compound substrate;
etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches; and
epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.
2. The method of claim 1 , wherein the III-V compound substrate comprises GaN.
3. The method of claim 1 , wherein the trenches each have a depth of about 0.8 μm.
4. The method of claim 1 , wherein the trenches each have a width of about 0.7 μm, and a width of the hardmask layer between two adjacent openings is about 3 μm.
5. The method of claim 1 , wherein a ratio of a width of an opening and a width of the hardmask layer between two adjacent openings is about 0.233.
6. The method of claim 1 , wherein the first set of openings comprises an array of hexagonal annulus patterns.
7. The method of claim 6 , wherein each side of a hexagonal annulus pattern is aligned with an m-plane of the III-V compound substrate.
8. The method of claim 1 , wherein the predetermined height is determined using an equation:
H =(√{square root over (3)}/2)* W,
wherein H is the predetermined height, and W is a width of a trench opening.
9. The method of claim 1 , wherein the alignment marks are characterized by an isosceles triangular shape having a base angle in a range between 58 degrees and 65 degrees in a cross-sectional view.
10. The method of claim 1 , wherein the second set of openings comprise an array of elongated openings arranged in parallel to each other configured to form a plurality of semiconductor fins.
11. The method of claim 10 , wherein the elongated openings each have a width in a range between about 0.2 μm and about 0.3 μm, a length in a range between about 100 μm and about 1000 μm, and a pitch between two adjacent elongated openings is in a range between about 1.9 μm and about 10 μm.
12. The method of claim 1 , wherein the III-V compound substrate comprises an n-GaN epitaxial layer, and the semiconductor layer comprises a p-GaN epitaxial layer.
13. The method of claim 1 , wherein epitaxially regrowing the semiconductor layer is self-limiting in the alignment mark region.
14. A semiconductor device comprising:
a III-V compound substrate comprising a device region and an alignment mark region including a plurality of trenches; and
a plurality of three-dimensional alignment marks, each of the plurality of three-dimensional alignment marks being disposed in one of the plurality of trenches in the alignment mark region, each of the plurality of three-dimensional alignment marks comprising a protrusion portion extending over a surface of the III-V compound substrate.
15. The semiconductor device of claim 14 , wherein each of the three-dimensional alignment marks comprises a hexagonal shaped, annular, alignment mark in plan view having a predetermined height and characterized by at least three directional growth surfaces.
16. The semiconductor device of claim 15 , wherein the protrusion portion has an isosceles triangle or trapezoid shape with a base angle in a range between 58 degrees and 65 degrees in a cross-sectional view.
17. The semiconductor device of claim 15 , wherein the protrusion portion has a shape of an isosceles triangle or a trapezoid with a base substantially flush with a surface of the III-V compound substrate in a cross-sectional view.
18. The semiconductor device of claim 17 , wherein the protrusion portion has a shape of an isosceles triangle and the predetermined height is determined using an equation:
H =(√{square root over (3)}/2)* W,
wherein H is the predetermined height, and W is a width of the base of the isosceles triangle.
19. The semiconductor device of claim 14 , wherein the III-V compound substrate comprises an N—GaN epitaxial layer, and the plurality of three-dimensional alignment marks comprise a p-GaN epitaxial layer.
20. The semiconductor device of claim 14 , wherein the device region comprises a plurality of semiconductor fins arranged in parallel to each other, wherein a regrown layer between each of the plurality of semiconductor fins has a regrowth surface lower than the protrusion portion of each of the plurality of three-dimensional alignment marks.