Method and system for fabrication of a vertical fin-based field effect transistor
A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.
1. A transistor comprising:
a substrate having a first surface and a second surface opposite the first surface;
a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region;
a semiconductor fin comprising a lower portion and an upper portion, wherein the lower portion protrudes from the graded doping region and contains a portion of the graded doping region, and wherein a metal compound layer is disposed in the upper portion of the semiconductor fin;
a source metal contact on the upper portion of the semiconductor fin;
a gate layer having a bottom portion directly contacting the graded doping region; and
a drain metal contact on the second surface of the substrate.
2. The transistor of claim 1 , wherein:
the semiconductor fin comprises a first dopant concentration;
the doped region of the drift region having a second dopant concentration that is lower than the first dopant concentration; and
the graded doping region of the drift region having a third dopant concentration linearly increasing from the second dopant concentration to the first dopant concentration.
3. The transistor of claim 2 , wherein the first dopant concentration is about 7.5×10 16 atoms/cm 3 , and the second dopant concentration is about 1×10 16 atoms/cm 3 .
4. The transistor of claim 1 , wherein:
the substrate comprises an N+ GaN layer;
the doped region of the drift region comprises an N− GaN layer;
the semiconductor fin comprises an N GaN layer; and
the gate layer comprise an In x Ga 1-x N layer, where 0<x<1.
5. The transistor of claim 4 , wherein a current first flows horizontally along a lateral surface of the bottom portion of the gate layer via a two-dimensional electron gas induced by polarization of the In x Ga 1-x N layer in a c-plane, then vertically in a direction toward the drain metal contact through the drift region.
6. The transistor of claim 1 , further comprising a polar c-plane interface between the gate layer and the graded doping region.
7. The transistor of claim 1 , wherein the source metal contact comprises a TiN/Ti/Al/Mo stack structure, wherein Al is deposited on Ti and Mo is deposited on Al.
8. The transistor of claim 1 , wherein the drift region has a thickness of about 12 μm, the graded doping region has a thickness of about 0.3 μm, and the semiconductor fin has a thickness of about 0.7 μm and a width of about 0.2 μm.
9. The transistor of claim 1 , further comprising a gate contact on a surface of the gate layer, wherein the gate contact comprises a Ni/Au/Mo stack structure, wherein Au is deposited on Ni and Mo is deposited on Au.
10. The transistor of claim 1 , wherein the upper portion of the semiconductor fin comprises sidewalls substantially parallel to each other.
11. The transistor of claim 10 , wherein the upper portion of the semiconductor fin is substantially perpendicular to the substrate.
12. The transistor of claim 1 , wherein the lower portion of the semiconductor fin comprises sidewalls non-parallel to each other.
13. The transistor of claim 12 , wherein the sidewalls of the lower portion of the semiconductor fin form an angle other than 90 degrees with the substrate.
14. The transistor of claim 1 , wherein the gate layer surrounds the semiconductor fin.