Semiconductor package with barrier layer

1. A packaged integrated circuit device, comprising:

a frame having a cavity therein;

an inner semiconductor chip within the cavity;

a lower re-distribution layer extending adjacent lower surfaces of the frame and the inner semiconductor chip, said lower re-distribution layer having an opening therein which at least partially exposes the lower surface of the inner semiconductor chip; and

a lower semiconductor chip adjacent the lower surface of the inner semiconductor chip, and within the opening in the lower re-distribution layer, which comprises: (i) an insulating layer covering the lower surface of the frame, (ii) a re-distribution pattern disposed on the insulating layer, and (iii) a barrier layer, which is disposed on the insulating layer and surrounds at least a portion of the lower semiconductor chip.

2. The device of claim 1 , wherein the barrier layer has a generally quadrangular rim shape when viewed from a top plan view perspective.

3. The device of claim 1 , wherein the lower semiconductor chip comprises:

a body disposed on the lower surface of the inner semiconductor chip;

a solder ball electrically connecting the body and the inner semiconductor chip; and

a mold layer extending between the body and the lower re-distribution layer.

4. The device of claim 3 , wherein the mold layer fills the opening and completely covers a side surface of the body while extending through the lower re-distribution layer.

5. The device of claim 4 , wherein an upper surface of the opening of the lower re-distribution layer comprises a first stepped surface, at which an upper surface of the barrier layer is partially exposed.

6. The device of claim 5 , wherein the upper surface of the opening of the lower re-distribution layer further comprises a second stepped surface at which an upper surface of the insulating layer is partially exposed.

7. The device of claim 1 , wherein the barrier layer has an inclined side surface.

8. The device of claim 1 , wherein an inner side surface of the insulating layer is inclined at an angle of about 60° to about 80°.

9. The device of claim 1 , further comprising:

an upper re-distribution layer disposed on the frame and the inner semiconductor chip, the upper-redistribution layer comprising a re-distribution pattern and an insulating layer; and

an upper semiconductor chip disposed on the upper re-distribution layer.

10. The device of claim 9 , further comprising a through-silicon-via, which extends through the frame and electrically connects the re-distribution pattern of the lower re-distribution layer and the re-distribution pattern of the upper re-distribution layer.

11. A packaged semiconductor device, comprising:

a frame having a cavity therein;

an inner semiconductor chip within the frame;

a lower re-distribution layer extending adjacent lower surfaces of the frame and the inner semiconductor chip, said lower re-distribution layer comprising a first insulating layer covering at least a portion of the lower surface of the inner semiconductor chip, a re-distribution pattern disposed on the first insulating layer, a barrier layer disposed on the first insulating layer, and a second insulating layer disposed on the barrier layer while partially exposing an upper surface of the barrier layer; and

a lower semiconductor chip adjacent the lower surface of the inner semiconductor chip;

wherein the first insulating layer, the re-distribution pattern, the barrier layer and the second insulating layer of the lower re-distribution layer comprise a stepped structure.

12. The device of claim 11 , wherein the stepped structure includes at least four stepped structures surrounding the lower semiconductor chip.

13. The device of claim 11 , wherein the lower semiconductor chip comprises:

a body disposed on the lower surface of the inner semiconductor chip;

a solder ball electrically connecting the body and the inner semiconductor chip; and

a mold layer extending between the body and the lower re-distribution layer.

14. The device of claim 13 , wherein an upper surface of the mold layer connects an edge of the lower re-distribution layer and an edge of the body of the lower semiconductor chip.

15. The device of claim 13 , wherein an upper surface of the mold layer has an inclination with respect to the lower surface of the inner semiconductor chip.

16. The device of claim 13 , wherein the re-distribution pattern is electrically connected to the inner semiconductor chip, and the barrier layer is electrically insulated from the inner semiconductor chip.

17. The device of claim 13 , wherein at least a portion of the lower semiconductor chip vertically overlaps with a portion of the lower re-distribution layer.

18. A packaged semiconductor device, comprising:

a frame having a cavity therein;

an inner semiconductor chip within the cavity within the frame;

a lower re-distribution layer extending on lower surfaces of the frame and on the inner semiconductor chip; and

a lower semiconductor chip extending on at least a portion of the lower surface of the inner semiconductor chip;

wherein the lower re-distribution layer has an opening therein, which at least partially exposes the lower surface of the inner semiconductor chip;

wherein the lower semiconductor chip extends within the opening;

wherein the lower re-distribution layer comprises:

a first insulating layer covering the lower surface of the frame;

a re-distribution pattern disposed on the first insulating layer;

a barrier layer disposed on the first insulating layer, and

a second insulating layer disposed on the barrier layer;

wherein the lower semiconductor chip comprises:

a body disposed on the lower surface of the inner semiconductor chip;

a solder ball electrically connecting the body and the inner semiconductor chip, and

a mold layer interposed between the body and the lower re-distribution layer;

wherein the barrier layer surrounds the lower semiconductor chip when viewed in a top view; and

wherein a portion of an upper surface of the barrier layer contacts the mold layer.

19. The packaged device of claim 18 , wherein a maximum horizontal distance between a side surface of the body and an inner side surface of the barrier layer is smaller than a minimum horizontal distance between the side surface of the body and an inner side surface of the second insulating layer when viewed from a top plan view perspective.

20. The packaged device of claim 18 , wherein the first insulating layer comprises a photo imageable dielectric (PID); and wherein the barrier layer comprises copper.