Memory layout for reduced line loading

1. A method for forming a memory device, the method comprising:

forming an array of access devices on a substrate, wherein the array of access devices comprises a plurality of rows, a first pair of columns, and a second pair of columns;

forming an interconnect structure over the array of access devices, wherein the interconnect structure comprises a plurality of wires and defines a first source line and a second source line, and wherein the first and second source lines are electrically coupled to access devices of the array respectively in the first and second pairs of columns;

depositing a dielectric layer over the array of access devices;

patterning the dielectric layer to form a plurality of openings elongated along the rows;

filling the openings with a conductive material to form a plurality of bridges in the openings, wherein the bridges at least partially define conductive paths electrically coupling the first source line to the second source line; and

forming an array of memory structures over the interconnect structure and the plurality of bridges, wherein the memory structures are respectively and electrically coupled to the access devices through the interconnect structure.

2. The method according to claim 1 , wherein the first and second source lines and the bridges have a common elevation above the substrate and are integrated together.

3. The method according to claim 1 , wherein the filling comprises:

depositing the conductive material filling the openings and covering the dielectric layer; and

performing a planarization into the conductive material until the dielectric layer is reached.

4. The method according to claim 1 , wherein the first and second source lines neighbor without intervening source lines.

5. The method according to claim 1 , wherein the openings have line-shaped top layouts that begin and end respectively and directly over the first pair of columns and the second pair of columns.

6. The method according to claim 1 , further comprising:

forming a plurality of additional wires over the array of memory structures, wherein the plurality of additional wires comprises a bit line wire laterally between the first and second source lines, and wherein the bit line wire is individual to a column in the array of access devices and is electrically coupled to memory structures overlying the column.

7. The method according to claim 1 , wherein the patterning defines a pair of additional openings simultaneously with the plurality of openings, wherein the additional openings are elongated respectively along the first pair of columns and the second pair of columns, wherein the openings are between and connect to the additional openings, and wherein the first and second source lines are formed respectively in the additional openings.

8. A method comprising:

forming an array of transistors overlying a substrate, wherein the array comprises a plurality of rows, a first column, and a second column;

depositing a first dielectric layer covering the array;

forming a plurality of first conductive features within the first dielectric layer and electrically coupled to the transistors;

depositing a second dielectric layer covering the first conductive features;

performing an etch selectively into the second dielectric layer to form a first trench and a second trench elongated respectively along the first and second columns, wherein the first and second trenches partially expose at least some of the first conductive features;

filling the first and second trenches with a conductive material to form a first wire and a second wire respectively in the first and second trenches; and

electrically coupling the first wire to the second wire.

9. The method according to claim 8 , wherein the plurality of first conductive features comprises contact vias extending from a top surface of the first dielectric layer respectively to the transistors.

10. The method according to claim 8 , wherein the first and second wires electrically couple to source/drain regions of the transistors through the first conductive features.

11. The method according to claim 8 , wherein the etch further defines a third trench extending from the first trench to the second trench, and wherein the method further comprises:

filling the third trench with the conductive material while filling the first and second trenches with the conductive material to define a conductive bridge electrically coupling the first wire to the second wire.

12. The method according to claim 8 , wherein the filling comprises:

depositing the conductive material in the first and second trenches and covering the second dielectric layer; and

removing the conductive material from atop the second dielectric layer.

13. The method according to claim 8 , wherein the method further comprises:

forming an array of memory structures overlying the first and second wires.

14. The method according to claim 8 , wherein the first and second trenches correspond to legs of a ladder-shaped openings formed in the second dielectric layer by the etch.

15. A method comprising:

forming an array of transistors overlying a substrate, wherein the array comprises a plurality of rows, a first column, and a second column;

depositing a first dielectric layer covering the array while forming a plurality of first metal features and a plurality of second metal features, wherein the first and second metal features are embedded in the first dielectric layer and electrically coupled to transistors of the array respectively in the first and second columns;

patterning the first dielectric layer to form an opening, wherein the opening has a first column segment and a second column segment extending respectively along the first and second columns, from one side of the array to an opposite side of the array, and respectively exposing at least some of the first and second metal features, and wherein the opening further has a bridge segment connecting the first column segment to the second column segment;

depositing a metal layer filling the opening and covering the first dielectric layer; and

performing a planarization into the metal layer to remove the metal layer from atop the first dielectric layer.

16. The method according to claim 15 , wherein first and second metal features exposed in the opening include contact vias extending to the substrate.

17. The method according to claim 15 , wherein the bridge segment of the opening begins and ends respectively and directly over the first and second columns.

18. The method according to claim 15 , wherein the patterning is performed by a photolithography/etching process.

19. The method according to claim 15 , wherein the patterning forms an additional opening at a common elevation above the substrate as the opening, wherein the opening extends in a closed path around the additional opening, wherein the metal layer is deposited filling the additional opening, and wherein the method further comprises:

forming a memory structure directly over and electrically coupled to a portion of the metal layer in the additional opening after the planarization.

20. The method according to claim 15 , further comprising:

forming a trench isolation structure (TIS) in the substrate, wherein the TIS has a first line-shaped segment, a second line-shaped segment, and a third line-shaped segment that are elongated in parallel along the first and second columns, wherein transistors of the array in the first column are between and border the first and second line-shaped segments of the TIS, wherein transistors of the array in the second column are between and border the second and third line-shaped segments of the TIS, and wherein the first and second column segments of the opening respectively overlie the first and third line-shaped segments of the TIS.