Microelectronic device assemblies and packages and related methods
Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
1. A microelectronic device assembly, comprising:
a microelectronic device having an active surface facing a substrate;
a single conductive material extending through each of a number of holes in a single, preformed dielectric film in direct contact with the active surface of the microelectronic device and the substrate, the single conductive material in the number of holes in contact with an array of bond pads on the active surface of the microelectronic device and terminal pads on the substrate; and
a stack of additional microelectronic devices on the microelectronic device, each additional microelectronic device having a separate, preformed dielectric film extending over a surface thereof and beyond at least one side of the stack of additional microelectronic devices, the separate, preformed dielectric films each carrying conductive traces extending from bond pads on the surfaces of the additional microelectronic devices to and in contact with conductive material-filled vias in the separate, preformed dielectric films located beyond the at least one side of the stack of additional microelectronic devices and extending to terminal pads on the substrate.
2. The microelectronic device assembly of claim 1 , wherein the array of bond pads are bond pads of an iRDL structure.
3. The microelectronic device assembly of claim 1 , wherein the preformed dielectric film is a NCF, a b-stage polyimide film or a PTFE film.
4. The microelectronic device assembly of claim 1 , wherein the conductive material comprises an Ag paste, a Cu paste, or a solder.
5. The microelectronic device assembly of claim 1 , further comprising a preformed die attach firm (DAF) or a preformed film over die (FOD) material directly between a back side of the microelectronic device and the stack of additional microelectronic devices on the microelectronic device.
6. The microelectronic device assembly of claim 1 , wherein bond pads of the additional microelectronic devices are located on active surfaces thereof facing away from the microelectronic device.
7. The microelectronic device assembly of claim 1 , further comprising discrete conductive elements on a surface of the substrate opposite the stack of additional microelectronic devices, the stack encapsulated in an epoxy molding compound.
8. A microelectronic device assembly comprising:
a stack of microelectronic devices on a substrate, each microelectronic device comprising TSVs extending through a thickness thereof between bond pads on an active surface and terminal pads on a back side thereof; and
preformed, discrete dielectric films interposed between and in direct contact with adjacent microelectronic devices of the stack, the preformed, discrete dielectric films comprising holes extending therethrough and aligned between bond pads and terminal pads of adjacent microelectronic devices of the stack, the holes filled with a single conductive material in contact with aligned bond pads and terminal pads of adjacent microelectronic components.
9. The microelectronic device assembly of claim 8 , wherein the preformed, discrete dielectric films comprise polymer films and the single conductive material comprises a conductive metal paste or a solder.
10. The microelectronic device assembly of claim 9 , wherein the polymer films comprise NCFs, b-stage polyimide films or PTFE films.
11. The microelectronic device assembly of claim 8 , further comprising an additional microelectronic device devoid of TSVs at a top of the stack of microelectronic devices and having bond pads in contact with conductive material in holes in a preformed dielectric film located between the additional microelectronic device and terminal pads of an adjacent, lower microelectronic device.
12. The microelectronic device assembly of claim 10 , further comprising an epoxy molding compound (EMC) encapsulating the stack of microelectronic devices and abutting a surface of the substrate, and discrete conductive elements on an opposing surface of the substrate.
13. A method comprising:
forming a reconstructed wafer or panel by placing singulated semiconductor dice in mutually spaced relationship and laminating a polymer film over active surfaces of the singulated semiconductor dice comprising bond pads;
forming via holes through the polymer film to expose bond pads on the active surfaces;
filling the via holes with conductive material;
singulating the semiconductor dice of the reconstructed panel or wafer through the polymer film;
inverting at least one semiconductor die and placing the inverted at least one semiconductor die on a substrate with conductive material-filled via holes aligned with terminal pads on the substrate; and
bonding the polymer film to the substrate with the conductive material in contact with the terminal pads.
14. The method of claim 13 , further comprising, before forming a reconstructed wafer or panel:
fabricating active circuitry on die locations of an active surface of a semiconductor substrate;
testing the semiconductor substrate to determine die locations of known good die (KGD); and
singulating the semiconductor substrate into individual KGD.
15. The method of claim 14 , further comprising, before testing the semiconductor substrate, forming iRDLs on each die location with traces to reroute bond pad locations on the active surface into an array of iRDL bond pads at locations to be exposed through the via holes in the polymer film.
16. The method of claim 13 , further comprising stacking additional semiconductor dice on the at least one semiconductor die placed on the substrate and operably coupling the additional semiconductor dice to terminal pads of the substrate by conductive vias extending through dielectric materials extending over active surfaces of the additional semiconductor dice to locations outside of a periphery of the additional semiconductor dice and in electrical communication with the additional semiconductor dice by traces carried by the dielectric materials and extending to bond pads on active surfaces of the additional semiconductor dice.
17. The method of claim 13 , further comprising, before forming a reconstructed wafer or panel:
fabricating active circuitry on die locations of an active surface of a semiconductor substrate and forming TSVs extending from terminal pads on a back side of the semiconductor substrate and the bond pads on the active surface;
testing the semiconductor substrate to determine die locations of known good die (KGD); and
singulating the semiconductor substrate into individual KGD.
18. The method of claim 17 , further comprising:
after inverting the at least one semiconductor die and placing the inverted at least one semiconductor die on the substrate with conductive material-filled via holes aligned with terminal pads on the substrate, inverting one or more additional semiconductor dice determined to be KGD and stacking the one or more additional semiconductor dice on the at least one semiconductor die with the via holes filled with conductive material of each additional semiconductor die aligned with terminal pads of a next lower adjacent semiconductor die; and
bonding the polymer film between adjacent semiconductor dice and the conductive material between and in contact with the bond pads and the terminal pads thereof substantially simultaneously with bonding the polymer film of the at least one semiconductor die to the substrate with the conductive material thereof to the terminal pads of the substrate.