Strobe-offset control circuit
A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.
1. An integrated circuit (IC) memory controller, comprising:
command generation circuitry to issue a calibration read command for a calibration read operation;
receiver circuitry to receive calibration read data from a memory device, the receiver circuitry to receive a strobe signal accompanying the read data;
phase adjustment circuitry coupled to the receiver circuitry, the phase adjustment circuitry, operative during the calibration read operation, to adjust a phase alignment between the strobe signal and the read data in response to a first control signal; and
wherein the first control signal is generated based on a comparison result of a data pattern of the calibration read data received by the memory controller during the calibration read operation.
2. The IC memory controller according to claim 1 , further comprising:
phase detection circuitry to detect a phase difference between the strobe signal and the calibration read data, and to generate an adjustment control signal based on the phase difference; and
wherein the first control signal indicates whether the adjustment control signal is valid.
3. The IC memory controller according to claim 1 , wherein:
the data pattern is based on a number of transitions exhibited by the calibration read data.
4. The IC memory controller according to claim 3 , wherein:
the comparison result is based on the number of transitions exhibited by the calibration read data compared with a second number of transitions exhibited by the strobe signal.
5. The IC memory controller according to claim 1 , wherein the command generation circuitry issues the calibration read command consistent with a dynamic random access memory (DRAM) protocol.
6. A method of operation in an integrated circuit (IC) memory controller, the method comprising:
receiving calibration read data from a memory device, and receiving a strobe signal accompanying the calibration read data, the receiving of the calibration read data and the strobe signal is in response to dispatching a calibration read command to the memory device for a calibration read operation;
generating a first control signal based on a comparison result of a data pattern of the calibration read data received by the memory controller; and
adjusting a phase alignment, during the calibration read operation, between the strobe signal and the calibration read data in response to the first control signal.
7. The method according to claim 6 , wherein the adjusting a phase alignment further includes:
detecting a phase difference between the strobe signal and the calibration read data;
generating an adjustment control signal based on the phase difference; and
wherein the first control signal indicates whether the adjustment control signal is valid.
8. The method according to claim 6 , wherein the data pattern is based on a number of transitions exhibited by the calibration read data.
9. The method according to claim 8 , further comprising:
comparing the number of transitions exhibited by the calibration read data with a second number of transitions exhibited by the strobe signal to generate the comparison result.
10. The method according to claim 6 , wherein:
the dispatching of the calibration read command is carried out consistent with a dynamic random access memory (DRAM) protocol.
11. An integrated circuit (IC) chip, comprising:
memory control circuitry, including
command generation circuitry to issue a calibration read command for a calibration read operation;
a receiver interface to receive calibration read data during the calibration read operation from a memory device, the receiver interface to receive a strobe signal accompanying the calibration read data;
adjustment circuitry coupled to the receiver interface, the adjustment circuitry operative during the calibration read operation to adjust a relative alignment between the strobe signal and the calibration read data in response to a first control signal; and
wherein the first control signal is generated based on a comparison result of a data pattern of the calibration read data received by the memory controller during the calibration read operation.
12. The IC chip according to claim 11 , further comprising:
a phase detector to detect a phase difference between the strobe signal and the calibration read data, and to generate an adjustment control signal to adjust the relative alignment based on the phase difference; and
wherein the first control signal indicates whether the adjustment control signal is valid.
13. The IC chip according to claim 11 , wherein:
the data pattern is based on a number of transitions exhibited by the calibration read data.
14. The IC chip according to claim 13 , wherein:
the comparison result is based on the number of transitions exhibited by the calibration read data compared with a second number of transitions exhibited by the strobe signal.