Memory device and method for forming thereof

1. A semiconductor device comprising:

a plurality of first memory cells in a memory region, each of the plurality of the first memory cells comprising a static random access memory (SRAM) cell, the static random access memory cell comprising a first pull-down transistor and a second pull-down transistor, the plurality of the first memory cells comprising a first memory cell; and

a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region, a first source/drain region of the first pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the first cut-off transistor, wherein a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.

2. The semiconductor device of claim 1 , wherein the power supply voltage is ground.

3. The semiconductor device of claim 1 , wherein a first source/drain region of the second pull-down transistor is electrically coupled to the first source/drain region of the first cut-off transistor.

4. The semiconductor device of claim 1 , wherein a gate electrode of the first cut-off transistor is electrically coupled to a word line.

5. The semiconductor device of claim 1 further comprising:

a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage.

6. The semiconductor device of claim 5 , wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line.

7. The semiconductor device of claim 1 , wherein the plurality of first memory cells comprises a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, wherein the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor.

8. The semiconductor device of claim 1 , wherein the plurality of first memory cells comprises a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, further comprising:

a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the second memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage.

9. The semiconductor device of claim 8 , wherein a gate electrode of the first cut-off transistor and the second cut-off transistor are coupled to a same control line.

10. A semiconductor device comprising:

a first memory cell in a memory array, the first memory cell comprising a static random access memory (SRAM) cell having a first pull-down transistor and a second pull-down transistor;

a dummy region along a boundary of the memory array;

a first cut-off transistor in the dummy region, the first cut-off transistor having a first source/drain electrically coupled to a first source/drain of the first pull-down transistor and a second source/drain electrically coupled to ground; and

a well pick-up region adjacent the dummy region, wherein the dummy region is interposed between the well pick-up region and the memory array.

11. The semiconductor device of claim 10 , wherein the first memory cell is a closest memory cell of memory cells connected to a same bit line to the dummy region.

12. The semiconductor device of claim 10 further comprising:

a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein the first cut-off transistor is not electrically interposed between the second memory cell and ground.

13. The semiconductor device of claim 10 further comprising:

a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first cut-off transistor.

14. The semiconductor device of claim 13 , wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line.

15. The semiconductor device of claim 10 further comprising:

a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor and having a second source/drain electrically coupled to ground.

16. The semiconductor device of claim 15 , wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line.

17. The semiconductor device of claim 10 further comprising:

a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor; and

a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor of the first memory cell and to a first source/drain of the second pull-down transistor of the second memory cell, the second cut-off transistor having a second source/drain electrically coupled to ground.

18. The semiconductor device of claim 17 , wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line.

19. A method of forming a semiconductor device, the method comprising:

forming a memory cell in a memory array, comprising:

forming a first pull-down transistor and a second pull-down transistor in a memory region of the memory array;

forming a first cut-off transistor in a dummy region of the memory array;

electrically connecting a first source/drain of the first cut-off transistor to a source/drain of the first pull-down transistor; and

electrically connecting a second source/drain of the first cut-off transistor to a power supply voltage.

20. The method of claim 19 further comprising:

forming a second cut-off transistor in the dummy region of the memory array;

electrically connecting a first source/drain of the second cut-off transistor to a source/drain of the second pull-down transistor; and

electrically connecting a second source/drain of the second cut-off transistor to the power supply voltage.