Transistor gates and method of forming
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.
1. A device comprising:
a first nanostructure;
a second nanostructure over the first nanostructure;
a first high-k gate dielectric disposed around the first nanostructure;
a second high-k gate dielectric being disposed around the second nanostructure; and
a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal, the first portion of the p-type work function metal filling an entire area between the first high-k gate dielectric and the second high-k gate dielectric, and the first portion of the p-type work function metal being a same material throughout.
2. The device of claim 1 , wherein the first portion of the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure.
3. The device of claim 1 , wherein the first portion of the p-type work function metal has a first thickness, wherein a second portion of the p-type work function metal on a sidewall of the first nanostructure has a second thickness, and wherein the first thickness is greater than the second thickness.
4. The device of claim 3 , wherein a ratio of the first thickness to the second thickness is no more than 2:1.
5. The device of claim 3 , wherein the second thickness is in a range of 30 Å to 50 Å.
6. The device of claim 3 , wherein a ratio of the second thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1.
7. The device of claim 6 , wherein the minimum width of the p-type work function metal is in a range of 10 nm to 180 nm.
8. The device of claim 1 , wherein the portion of the gate electrode between the first nanostructure and the second nanostructure is free of any barrier layers.
9. The device of claim 1 , wherein the gate electrode further comprises an adhesion layer over the p-type work function metal, the adhesion layer does not extend between the first nanostructure and the second nanostructure.
10. The device of claim 1 , wherein a ratio of a height of the first nanostructure to a width of the first nanostructure is in a range of 0.05 to 4.
11. A transistor comprising:
a first nanostructure over a semiconductor substrate;
a second nanostructure over the first nanostructure;
a gate dielectric surrounding the first nanostructure and the second nanostructure; and
a gate electrode over the gate dielectric, wherein the gate electrode comprises:
a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric on the first nanostructure to a second portion of the gate dielectric on the second nanostructure, wherein the p-type work function metal has a first thickness on a top surface of the second nanostructure and a second thickness between the first nanostructure and the second nanostructure, wherein the first thickness is less than the second thickness;
an adhesion layer over the p-type work function metal; and
a fill metal over the adhesion layer.
12. The transistor of claim 11 , wherein the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure.
13. The transistor of claim 11 , wherein the p-type work function metal comprises titanium nitride.
14. The transistor of claim 11 further comprising an interfacial layer under the gate dielectric, the interfacial layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material.
15. A method comprising:
depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure; and
depositing a p-type work function metal over the gate dielectric, wherein depositing the p-type work function metal comprises:
depositing a first portion of the p-type work function metal on a top surface of the second nanostructure and a second portion of the p-type work function metal on a bottom surface of the first nanostructure; and
continuing to deposit the p-type work function metal until the first portion of the p-type work function metal merges with the second portion of the p-type work function metal.
16. The method of claim 15 , further comprising:
depositing an adhesion layer over the p-type work function metal; and
depositing a fill metal over the adhesion layer.
17. The method of claim 16 , wherein depositing the p-type work function metal comprises depositing the p-type work function metal to have:
a first thickness between the first nanostructure and the second nanostructure; and
a second thickness on a sidewall of the first nanostructure, the first thickness is greater than the second thickness.
18. The method of claim 17 , wherein a ratio of the first thickness to the second thickness is no more than 2:1.
19. The method of claim 15 , wherein depositing the p-type work function metal comprises forming a seam between the first portion of the p-type work function metal and the second portion of the p-type work function metal.
20. The method of claim 15 , wherein the p-type work function metal is titanium nitride.