IP Library › Granted Patent US 12,349,410
Granted Patent B2
US 12,349,410 · App. 18/414,753 · Granted Jul 1, 2025

Nanostructure field-effect transistor (NANO-FET) with gates including a seam in p-type work function metal between nanostructures and methods of forming

Inventors: Hsin-Yi Lee (Hsinchu, TW); Ji-Cheng Chen (Hsinchu, TW); Cheng-Lung Hung (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D30/6735H10D30/0243H10D30/6212H10D64/01H10D30/6739H10D62/121
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,349,410
App. No.
18/414,753
Granted
Jul 1, 2025
Kind
B2
Abstract

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

Claims (35)

1. A device comprising:

a first semiconductor structure over a semiconductor substrate;

a second semiconductor structure over and separated from the first semiconductor structure by a spacing;

a first gate dielectric around the first semiconductor structure;

a second gate dielectric around the second semiconductor structure; and

a p-type work function metal between the first gate dielectric and the second gate dielectric, wherein the spacing that separates the first semiconductor structure from the second semiconductor structure is completely filled by the first gate dielectric, the second gate dielectric, and the p-type work function metal, wherein a first portion of the p-type work function metal has a first thickness in the spacing that separates the first semiconductor structure from the second semiconductor structure, wherein a ratio of the first thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1, the minimum width of the p-type work function metal being measured in a direction perpendicular to a direction in which the first thickness is measured.

2. The device of claim 1 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

3. The device of claim 1 , wherein a second portion of the p-type work function metal on a sidewall of the first semiconductor structure has a second thickness, and wherein the first thickness is greater than the second thickness.

4. The device of claim 3 , wherein the second thickness is at least one half of the first thickness.

5. The device of claim 3 , wherein the second thickness is in a range of 30 Å to 50 Å.

6. The device of claim 1 , wherein the p-type work function metal comprises a seam between the first semiconductor structure and the second semiconductor structure.

7. The device of claim 1 , wherein the minimum width of the p-type work function metal is in a range of 10 nm to 180 nm.

8. The device of claim 1 , wherein the p-type work function metal has the minimum width in the spacing between the first semiconductor structure and the second semiconductor structure.

9. The device of claim 1 , further comprising an adhesion layer over the p-type work function metal, wherein the adhesion layer does not extend between the first semiconductor structure and the second semiconductor structure.

10. The device of claim 9 , further comprising a fill metal over the adhesion layer.

11. A transistor comprising:

a first nanostructure over a semiconductor substrate;

a second nanostructure over the first nanostructure;

a gate dielectric surrounding the first nanostructure and the second nanostructure; and

a gate electrode over the gate dielectric, wherein the gate electrode comprises:

a p-type work function metal, wherein the p-type work function metal extends a first distance from a top surface of the gate dielectric on the first nanostructure to a bottom surface of the gate dielectric on the second nanostructure, wherein the p-type work function metal has a seam between the first nanostructure and the second nanostructure, wherein the seam extends a second distance from a first sidewall of the p-type work function metal to a second sidewall of the p-type work function metal, and wherein a ratio of the first distance to the second distance is in a range of 0.03 to 1; and

a fill metal over the p-type work function metal.

12. The transistor of claim 11 , wherein the p-type work function metal has a thickness on a top surface of the second nanostructure, wherein the first distance is greater than the thickness.

13. The transistor of claim 11 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

14. The transistor of claim 11 , wherein the gate electrode further comprises an adhesion layer between the fill metal and the p-type work function metal.

15. A method comprising:

depositing a first gate dielectric material around a first nanostructure and a second gate dielectric material around a second nanostructure, the first nanostructure being disposed over the second nanostructure, the first gate dielectric material being spaced apart from the second gate dielectric material by a gap having a first height; and

depositing a p-type work function metal on the first gate dielectric material and the second gate dielectric material, wherein depositing the p-type work function metal comprises depositing the p-type work function metal until the p-type work function metal fills an entirety of the gap, wherein depositing the p-type work function metal comprises depositing the p-type work function metal to have a minimum width between the first nanostructure and the second nanostructure, wherein a ratio of the first height to the minimum width is in a range of 0.03 to 1.

16. The method of claim 15 , further comprising:

depositing an adhesion layer over the p-type work function metal; and

depositing a fill metal over the adhesion layer.

17. The method of claim 15 , wherein depositing the p-type work function metal further comprises depositing the p-type work function metal to have a seam between the first nanostructure and the second nanostructure.

18. The method of claim 17 , wherein the minimum width of the p-type work function metal is a width of the seam.

19. The method of claim 15 , wherein depositing the p-type work function metal comprises depositing the p-type work function metal to have a thickness in a range of 30 Å to 50 Å on a sidewall or a top surface of the first nanostructure.

20. The method of claim 15 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

Continuity (4)
Continuation 17717382 · Apr 11, 2022
Continuation 16943110 · Jul 30, 2020
Provisional Application 63038970 · Jun 15, 2020
Related Publication 20240154016A1 · May 9, 2024
References Cited (27)
US 9997519B1 · Bao et al. · 2018 [cited by applicant]
US 10319846B1 · Ando et al. · 2019 [cited by applicant]
US 10510620B1 · Chanemougame et al. · 2019 [cited by applicant]
US 10700064B1 · Zhang et al. · 2020 [cited by applicant]
US 11302793B2 · Lee et al. · 2022 [cited by applicant]
US 11916124B2 · Lee · 2024 [cited by examiner]
US 20150053912A1 · Chiang et al. · 2015 [cited by applicant]
US 20160336420A1 · Chou et al. · 2016 [cited by applicant]
US 20170104060A1 · Balakrishnan et al. · 2017 [cited by applicant]
US 20170179248A1 · Pawlak · 2017 [cited by applicant]
US 20180350935A1 · Bao et al. · 2018 [cited by applicant]
US 20190103472A1 · Cheng et al. · 2019 [cited by applicant]
US 20190237336A1 · Wang et al. · 2019 [cited by applicant]
US 20200020692A1 · Ching et al. · 2020 [cited by applicant]
US 20200035567A1 · Chanemougame et al. · 2020 [cited by applicant]
US 20200083327A1 · Cheng et al. · 2020 [cited by applicant]
US 20200119167A1 · More et al. · 2020 [cited by applicant]
US 20200243399A1 · Bao et al. · 2020 [cited by applicant]
US 20200266060A1 · Cheng et al. · 2020 [cited by applicant]
US 20210217846A1 · Hashemi et al. · 2021 [cited by applicant]
US 20230377984A1 · Cheng et al. · 2023 [cited by applicant]
KR 101517700B1 · 2015 [cited by applicant]
KR 20160134443A · 2016 [cited by applicant]
KR 20190038224A · 2019 [cited by applicant]
TW 201735160A · 2017 [cited by applicant]
TW 202008436A · 2020 [cited by applicant]
TW 202013522A · 2020 [cited by applicant]