Semiconductor device and method
View Patent ↗Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of nanostructures stacked over a semiconductor substrate, wherein each one of the plurality of nanostructures comprises:
forming a stack of a first material and a second material different from the first material over the first material;
forming a core region from the first material;
forming a sheath region surrounding the first material from the second material, the second material having a thickness of less than or equal to 2 nanometers;
forming a gate dielectric extending between a first one of the plurality of nanostructures and a second one of the plurality of nanostructures;
forming a gate electrode extending between the first one of the plurality of nanostructures and the second one of the plurality of nanostructures; and
forming a second plurality of second nanostructures over the semiconductor substrate, wherein the forming the second plurality of second nanostructures comprises:
forming a second core region of the second material; and
forming a second sheath region surrounding the first material, the second sheath region comprising a third material different from the second material.
2. The method of claim 1 , wherein the first material is silicon.
3. The method of claim 2 , wherein the second material is silicon germanium.
4. The method of claim 1 , wherein the forming the sheath region forms the second material to a thickness of less than or equal to 1 nanometer.
5. The method of claim 1 , wherein the forming the sheath region forms the second material to a thickness of less than or equal to 0.96 nanometers.
6. The method of claim 1 , wherein the plurality of nanostructures is part of a gate all-around transistor.
7. A method of manufacturing a semiconductor device, the method comprising:
forming a gate dielectric around a first semiconductor material, wherein a second semiconductor material separates the first semiconductor material from the gate dielectric, the second semiconductor material being different from the first semiconductor material and having a thickness of less than 2 nanometers, the second semiconductor material comprising silicon; and
forming a gate electrode surrounding the gate dielectric around the first semiconductor material.
8. The method of claim 7 , wherein the second semiconductor material has a thickness of less than 1 nanometer.
9. The method of claim 7 , wherein the second semiconductor material has a thickness of less than 0.96 nanometers.
10. The method of claim 7 , wherein the first semiconductor material is silicon.
11. The method of claim 10 , wherein the second semiconductor material comprises germanium.
12. The method of claim 7 , wherein the forming the gate electrode forms a gate all-around device.
13. A method of manufacturing a semiconductor device, the method comprising:
forming a first nanostructure, the first nanostructure comprising:
a first material; and
a first diffusion interface surrounding the first material, the first diffusion interface having a thickness that is greater than zero and less than or equal to 2 nanometers, wherein the first diffusion interface comprises atoms from the first material; and
forming a first gate electrode around the first nanostructure.
14. The method of claim 13 , wherein the thickness is less than or equal to 1 nanometer.
15. The method of claim 13 , wherein the thickness is less than or equal to 0.96 nanometers.
16. The method of claim 13 , wherein the first material is silicon.
17. The method of claim 16 , wherein the first diffusion interface comprises germanium.
18. The method of claim 13 , wherein the first material has a first diameter of between about 3 nm and about 20 nm.
19. The method of claim 13 , wherein the first material has a first diameter of between about 3 nm and about 8 nm.
20. The method claim 13 , wherein the first nanostructure is part of a gate all-around transistor.