Transistor gates and methods of forming
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.
1. A device comprising:
a first nanostructure;
a second nanostructure over the first nanostructure;
a first gate dielectric material around the first nanostructure;
a second gate dielectric material around the second nanostructure; and
a p-type work function metal extending continuously from the first gate dielectric material to the second gate dielectric material in a region between the first nanostructure and the second nanostructure, wherein the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure, wherein a first portion of the p-type work function metal has a first thickness, wherein the first portion of the p-type work function metal is disposed in the region between the first nanostructure and the second nanostructure, wherein a ratio of the first thickness to a minimum width of the p-type work function metal is in a range of 0.03 to 1, the minimum width of the p-type work function metal being measured in a direction perpendicular to a direction in which the first thickness is measured.
2. The device of claim 1 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.
3. The device of claim 1 , wherein a second portion of the p-type work function metal on a sidewall of the first nanostructure has a second thickness, and wherein the first thickness is greater than the second thickness.
4. The device of claim 3 , wherein a ratio of the first thickness to the second thickness is no more than 2:1.
5. The device of claim 3 , wherein the second thickness is in a range of 30 Å to 50 Å.
6. The device of claim 1 , wherein the minimum width of the p-type work function metal is in a range of 10 nm to 180 nm.
7. The device of claim 1 , wherein the p-type work function metal has the minimum width in the region between the first nanostructure and the second nanostructure.
8. The device of claim 1 , further comprising an adhesion layer over the p-type work function metal, wherein the adhesion layer does not extend between the first nanostructure and the second nanostructure.
9. A transistor comprising:
a first nanostructure over a semiconductor substrate;
a second nanostructure over the first nanostructure;
a gate dielectric surrounding the first nanostructure and the second nanostructure; and
a gate electrode over the gate dielectric, wherein the gate electrode comprises:
a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric on the first nanostructure to a second portion of the gate dielectric on the second nanostructure, wherein the p-type work function metal has a first thickness between the first nanostructure and the second nanostructure, wherein the p-type work function metal has a minimum width between the first nanostructure and the second nanostructure, wherein a ratio of the first thickness to the minimum width is in a range of 0.03 to 1, wherein the minimum width is measured in a first direction parallel to a top surface of the semiconductor substrate, and wherein the first thickness is measured in a second direction perpendicular to the first direction; and
a fill metal over the p-type work function metal.
10. The transistor of claim 9 , wherein the p-type work function metal has a second thickness on a top surface of the second nanostructure, wherein the first thickness is greater than the second thickness.
11. The transistor of claim 9 , wherein the p-type work function metal comprises a seam between the first nanostructure and the second nanostructure.
12. The transistor of claim 9 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.
13. The transistor of claim 9 further comprising an interfacial layer under the gate dielectric, the interfacial layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material.
14. A method comprising:
depositing a first gate dielectric material around a first nanostructure and a second gate dielectric material around a second nanostructure, the first nanostructure being disposed over the second nanostructure, the first gate dielectric material being spaced apart from the second gate dielectric material by a gap; and
depositing a p-type work function metal on the first gate dielectric material and the second gate dielectric material, wherein depositing the p-type work function metal comprises continuously depositing the p-type work function metal until a seam is defined between the first gate dielectric material and the second gate dielectric material and the p-type work function metal fills an entirety of the gap separating the first gate dielectric material and the second gate dielectric material, wherein depositing the p-type work function metal comprises depositing the p-type work function metal to have:
a first thickness between the first nanostructure and the second nanostructure; and
a minimum width between the first nanostructure and the second nanostructure, wherein a ratio of the first thickness to the minimum width is in a range of 0.03 to 1, and wherein the minimum width is measured in a first direction, and wherein the first thickness is measured in a second direction perpendicular to the first direction.
15. The method of claim 14 , further comprising:
depositing an adhesion layer over the p-type work function metal; and
depositing a fill metal over the adhesion layer.
16. The method of claim 14 , wherein depositing the p-type work function metal further comprises depositing the p-type work function metal to have:
a second thickness on a sidewall of the first nanostructure, the first thickness being greater than the second thickness.
17. The method of claim 16 , wherein a ratio of the first thickness to the second thickness is no more than 2:1.
18. The method of claim 14 , further comprising depositing a first interfacial material around the first nanostructure and a second interfacial material around the second nanostructure prior to depositing the first gate dielectric material and the second gate dielectric material.
19. The method of claim 14 , wherein the p-type work function metal comprises titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.