Multi-gate semiconductor device

1. A semiconductor structure, comprising:

a substrate;

first nanostructures and second nanostructures formed over the substrate;

a first source/drain structure formed adjacent to the first nanostructures;

a second source/drain structure formed adjacent to the second nanostructures;

a first contact plug formed over the first source/drain structure;

a second contact plug formed over the second source/drain structure,

wherein a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.

2. The semiconductor structure as claimed in claim 1 , wherein the first source/drain structure covers sidewalls of the first nanostructures and extends between neighboring first nanostructures.

3. The semiconductor structure as claimed in claim 1 , wherein the second source/drain structure surrounds portions of the second nanostructures.

4. The semiconductor structure as claimed in claim 1 , further comprising:

a first gate structure surrounding the first nanostructures; and

a second gate structure surrounding the second nanostructures,

wherein a bottom surface of the first gate structure is higher than the bottom portion of the first contact plug.

5. The semiconductor structure as claimed in claim 1 , further comprising:

a first silicide layer formed over the first source/drain structure, wherein a bottom portion of the first silicide layer is lower than the bottom portion of the first nanostructures.

6. The semiconductor structure as claimed in claim 5 , further comprising:

a second silicide layer formed over the second source/drain structure, wherein an interface between the first silicide layer and the first source/drain structure is greater than an interface between the second silicide layer and the second source/drain structure.

7. The semiconductor structure as claimed in claim 1 , wherein a height of the first contact plug is greater than a height of the second contact plug.

8. A semiconductor structure, comprising:

a substrate;

first nanostructures and second nanostructures formed over the substrate;

a first gate structure surrounding the first nanostructure and a second gate structure surrounding first portions of the second nanostructures;

a first source/drain semiconductor layer formed adjacent to the first gate structure;

a second source/drain semiconductor layer surrounding second portions of the second nanostructures;

a first contact plug formed over the first source/drain semiconductor layer; and

a second contact plug formed over the second source/drain semiconductor layer,

wherein the first contact plug extends below a topmost surface of the first nanostructures.

9. The semiconductor structure as claimed in claim 8 , wherein a bottommost of the second contact plug is higher than the second nanostructures.

10. The semiconductor structure as claimed in claim 8 , further comprising:

first inner spacers separating the first gate structure and the first source/drain semiconductor layer,

wherein the first contact plug has a first portion level with the first inner spacers and has a second portion level with the first nanostructures, and a first lateral width of the first portion is greater than a second lateral width of the second portion.

11. The semiconductor structure as claimed in claim 8 , wherein a top surface of the first contact plug is substantially level with a top surface of the second contact plug, and a bottom surface of the first contact plug is lower than a bottom surface of the second contact plug.

12. The semiconductor structure as claimed in claim 8 , further comprising:

a first silicide layer formed over the first source/drain semiconductor layer; and

a second silicide layer formed over the second source/drain semiconductor layer,

wherein the first silicide layer extends lower than the second silicide layer.

13. The semiconductor structure as claimed in claim 12 , further comprising:

first inner spacers separating the first gate structure and the first source/drain semiconductor layer,

wherein the first silicide layer extends along sidewalls of the first nanostructures and sidewalls of the first inner spacers.

14. A semiconductor structure, comprising:

a substrate;

a first fin structure and a second fin structure protruding from the substrate;

first nanostructures formed over the first fin structure;

second nanostructures formed over the second fin structure;

a first gate structure wrapping around the first nanostructure;

a second gate structure wrapping around the second nanostructures;

a first source/drain layer formed adjacent to the first gate structure and in direct contact with the first nanostructures; and

a second source/drain layer formed adjacent to the first gate structure and in direct contact with the second nanostructures,

wherein a bottom surface of the first source/drain layer is lower than a bottommost nanostructure of the first nanostructures and is also lower than a bottom surface of the second source/drain layer.

15. The semiconductor structure as claimed in claim 14 , further comprising:

a first silicide layer formed over the first source/drain layer; and

a second silicide layer formed over the second silicide layer,

wherein a bottom surface of the first silicide is lower than a bottom surface of the second silicide.

16. The semiconductor structure as claimed in claim 14 , wherein the bottom surface of the first silicide layer is lower than a top surface of the first nanostructures.

17. The semiconductor structure as claimed in claim 14 , wherein the bottom surface of the second silicide layer is higher than a top surface of the second nanostructures.

18. The semiconductor structure as claimed in claim 14 , further comprising:

a first contact plug formed over the first source/drain layer; and

a second contact plug formed over the second source/drain layer,

wherein the first contact plug extends below a top surface of the first nanostructures.

19. The semiconductor structure as claimed in claim 14 , wherein the second nanostructures further comprises extending portions extend into the second source/drain layer, and the extending portions of the second nanostructures are wrapped by the second source/drain layer.

20. The semiconductor structure as claimed in claim 14 , wherein the second gate structure has a curved bottom surface.