GATE CONTACT INTERLAYER FOR HEMT DEVICES WITH SELF-ALIGNED ELECTRODES
A HEMT is described in which a gate contact interlayer is included between a surface dielectric and a gate contact. Further, source, drain, and gate contacts may be self-aligned and formed using a single or same metal and metallization process. A gate may be formed in contact with, and covering a portion of, a barrier layer of the HEMT, with a gate contact formed in contact with the gate. The gate contact interlayer may be formed between a surface dielectric formed on the barrier layer and at least a portion of the gate contact.
1 . A High Electron Mobility Transistor (HEMT), comprising:
a source region;
a source contact connected to the source region;
a drain region;
a drain contact connected to the drain region;
a channel layer extending between the source region and the drain region;
a barrier layer formed in contact with the channel layer, and extending between the source region and the drain region;
a gate formed in contact with, and covering at least a portion of, the barrier layer;
a gate contact connected to the gate;
a surface dielectric formed on the barrier layer, between the source contact and the gate contact, and between the drain contact and the gate contact; and
a gate contact interlayer disposed between the surface dielectric and at least a portion of the gate contact.
2 . The HEMT of claim 1 , wherein the gate contact interlayer is disposed between the gate contact and the gate.
3 . The HEMT of claim 1 , wherein the gate contact forms an Ohmic contact with the gate.
4 . The HEMT of claim 1 , further comprising:
a source contact interlayer disposed between the source contact and the surface dielectric; and
a drain contact interlayer disposed between the drain contact and the surface dielectric.
5 . The HEMT of claim 4 , wherein the source contact interlayer is disposed along an entire interface of the source contact and the surface dielectric, and the drain contact interlayer is disposed along an entire interface of the drain contact and the surface dielectric.
6 . The HEMT of claim 1 , wherein the source contact, the drain contact, and the gate contact are self-aligned.
7 . The HEMT of claim 1 , wherein the source contact, the drain contact, and the gate contact are formed of the same metallization.
8 . The HEMT of claim 1 , wherein the gate contact interlayer includes a metal barrier layer.
9 . The HEMT of claim 1 , further comprising:
a second surface dielectric formed on the surface dielectric and on the gate contact;
a source field plate connected to the source contact that extends over at least a portion of the second surface dielectric and over at least a portion of the gate contact; and
a source field plate interlayer between the source field plate and the second surface dielectric.
10 . A gate structure for a High Electron Mobility Transistor (HEMT) device, comprising:
a gate formed in contact with, and covering a portion of, a barrier layer of the HEMT;
a gate contact formed in contact with the gate; and
a gate contact interlayer formed between a surface dielectric formed on the barrier layer and at least a portion of the gate contact.
11 . The gate structure of claim 10 , wherein the gate contact interlayer is disposed between the gate contact and the gate.
12 . The gate structure of claim 11 , wherein the gate contact forms an Ohmic contact with the gate.
13 . The gate structure of claim 12 , wherein the gate includes pGaN, and a treated surface between the pGaN and the gate contact interlayer is treated to reduce a p-type donor concentration thereof.
14 . The gate structure of claim 10 , wherein the gate contact is self-aligned with a source contact and a drain contact of the HEMT.
15 . The gate structure of claim 10 , wherein the gate contact interlayer includes a metal barrier layer.
16 . A method of making a High Electron Mobility Transistor (HEMT), comprising:
forming a layer stack that includes at least a channel layer and a barrier layer adjacent to the channel layer and forming a heterojunction at which a current channel is defined in the channel layer between a source region and a drain region of the HEMT;
forming a gate on the barrier layer;
forming a surface dielectric on a portion of the gate, and on the barrier layer;
forming a contact interlayer on the surface dielectric;
etching the surface dielectric to provide contact openings therein;
etching the contact interlayer to form a gate contact interlayer disposed on the surface dielectric; and
forming, in the contact openings, a source contact in contact with the source region, a drain contact in contact with the drain region, and a gate contact in contact with the gate and having at least a portion disposed on the gate contact interlayer.
17 . The method of claim 16 , wherein etching the surface dielectric comprises:
forming the contact interlayer prior to the etching the surface dielectric; and
etching the contact interlayer and the surface dielectric together to form the contact openings.
18 . The method of claim 16 , wherein etching the surface dielectric comprises:
etching the surface dielectric to form a gate contact opening of the contact openings;
forming the contact interlayer subsequent to the etching the surface dielectric; and
etching the contact interlayer to remove the contact interlayer from a source contact opening and a drain contact opening of the contact openings, while leaving the contact interlayer within the gate contact opening of the contact openings and disposed on the gate.
19 . The method of claim 16 , wherein the source contact, the drain contact, and the gate contact are formed using a self-aligned process and using the same metallization.
20 . The method of claim 16 , comprising:
forming a source contact interlayer disposed between the source contact and the surface dielectric; and
a drain contact interlayer disposed between the drain contact and the surface dielectric.