Common-mode transient immunity (CMTI) circuit and method of operation therefor
A CMTI circuit includes a first detector that receives one or more output signals from an oscillator and a first enable signal and generates a first detection signal when the received output signals are determined to be substantially not oscillating at a first time. The CMTI circuit further includes a first activation signal generator that generates a first activation signal in response to the first detection signal to resume oscillation of the output signals.
1. A common-mode transient immunity (CMTI) circuit, comprising:
a first detector configured to receive at least one output signal from an oscillator and a first enable signal and generate a first detection signal when the at least one output signal is determined to be substantially not oscillating at a first time; and
a first activation signal generator configured to generate a first activation signal in response to the first detection signal to resume oscillation of the at least one output signal.
2. The CMTI circuit of claim 1 , wherein the first activation signal generator generates the first activation signal having a first value to adjust a magnitude of a tail current of the oscillator by a first magnitude.
3. The CMTI circuit of claim 2 , further comprising:
a second detector configured to receive the at least one output signal and a second enable signal and generate a second detection signal when the at least one output signal is determined to be substantially not oscillating at a second time; and
a second activation signal generator configured to generate a second activation signal in response to the second detection signal to resume the oscillation.
4. The CMTI circuit of claim 3 , wherein the second activation signal generator generates the second activation signal having a second value to adjust the magnitude of the tail current of the oscillator by a second magnitude.
5. The CMTI circuit of claim 4 , wherein the first activation signal has the first value during a first time interval and the second activation signal has the second value during a second time interval, the second time interval being in a range of 10% to 50% of the first time interval.
6. The CMTI circuit of claim 4 , wherein the first activation signal generator includes:
a first switching device having a control terminal that receives the first detection signal and a first terminal coupled to a power supply voltage;
a first RC circuit coupled to a second terminal of the first switching device and including a first resistor and a first capacitor coupled in parallel; and
a first comparator coupled to the first RC circuit and generating the first activation signal,
wherein the first value and the second value are a same logic value.
7. The CMTI circuit of claim 6 , wherein the second activation signal generator includes:
a second switching device having a control terminal that receives the second detection signal and a first terminal coupled to the power supply voltage;
a second RC circuit coupled to a second terminal of the second switching device and including a second resistor and a second capacitor coupled in parallel; and
a second comparator coupled to the second RC circuit and generating the second activation signal.
8. The CMTI circuit of claim 4 , wherein the first activation signal generator increases the magnitude of the tail current of the oscillator by the first magnitude and the second activation signal generator increases the magnitude of the tail current of the oscillator by the second magnitude, the second magnitude being in a range of 80% to 120% of the first magnitude.
9. The CMTI circuit of claim 3 , further comprising a delay circuit configured to delay the first activation signal to generate the second enable signal.
10. The CMTI circuit of claim 1 , wherein the at least one output signal includes a first output signal and a second output signal, and the first detector determines that the oscillator has substantially stopped the oscillation when one or both of the first output signal and the second output signal become substantially equal to a power supply voltage coupled to the oscillator.
11. A system, comprising:
a transmitter configured to modulate a data input signal using an oscillator to generate at least one output signal, the transmitter including a first bleeder circuit configured to generate a first detection signal in response to a first enable signal when the at least one output signal is determined to be substantially not oscillating at a first time and generate a first activation signal in response to the first detection signal to resume oscillation of the at least one output signal;
a galvanic isolator configured to transfer the at least one output signal from the transmitter; and
a receiver configured to generate a data output signal in response to the transferred at least one output signal.
12. The system of claim 11 , wherein the oscillator includes a first current source configured to generate a first tail current in response to the data input signal and a second current source configured to generate a second tail current in response to the first activation signal.
13. The system of claim 12 , wherein the transmitter further includes a second bleeder circuit configured to:
delay the first activation signal to generate a second enable signal;
generate a second detection signal in response to the second enable signal when the at least one output signal is determined to be substantially not oscillating at a second time; and
generate a second activation signal in response to the second detection signal to resume the oscillation.
14. The system of claim 13 , wherein the oscillator further includes a third current source configured to generate a third tail current in response to the second activation signal.
15. The system of claim 11 , wherein:
the transmitter further includes a first inductor, the galvanic isolator includes a first winding and a second winding, and the receiver includes a second inductor, and
the transmitter and the first winding of the galvanic isolator are integrated in a first chip and the receiver and the second winding of the galvanic isolator is integrated in a second chip.
16. The system of claim 11 , wherein the at least one output signal includes a first output signal and a second output signal, and the first bleeder circuit determines that the oscillator has substantially stopped the oscillation when one or both of the first output signal and the second output signal become substantially equal to a power supply voltage coupled to the oscillator.
17. A method for controlling data transfer, the method comprising:
modulating a data input signal using an oscillator to generate at least one output signal;
generating a first detection signal in response to a first enable signal when the at least one output signal is determined to be substantially not oscillating at a first time; and
generating a first activation signal in response to the first detection signal to resume oscillation of the at least one output signal.
18. The method of claim 17 , further comprising adjusting a magnitude of a tail current by a first magnitude in response to the first activation signal when the first detection signal indicates that the at least one output signal is substantially not oscillating at the first time.
19. The method of claim 18 , further comprising:
delaying the first activation signal to generate a second enable signal;
generating a second detection signal in response to the second enable signal when the at least one output signal is substantially not oscillating at a second time; and
generating a second activation signal in response to the second detection signal to resume the oscillation.
20. The method of claim 19 , further comprising adjusting the magnitude of the tail current by a second magnitude in response to the second activation signal when the second detection signal indicates that the at least one output signal is substantially not oscillating at the second time.