Up-diffusion suppression in a power MOSFET
A substrate for fabricating a MOSFET device includes a first epitaxial layer disposed on a silicon wafer. The silicon wafer is doped with a first dopant. A second epitaxial layer is disposed on the first epitaxial layer. An ion-implanted capping layer is disposed in the first epitaxial layer. The ion-implanted capping layer is doped with a second dopant. The first dopant has a diffusion coefficient in silicon higher than a diffusion coefficient of the second dopant in silicon. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer into the second epitaxial layer.
1. A substrate for fabricating a vertical MOSFET device, the substrate comprising:
a silicon wafer;
a first epitaxial layer including an ion-implanted capping layer disposed on the silicon wafer, the silicon wafer and the ion-implanted capping layer being doped with dopants of a same conductivity type, the silicon wafer being doped with a first dopant to form a drain region of the vertical MOSFET device, the ion-implanted capping layer being doped with a second dopant, the first dopant having a higher diffusivity in silicon than a lower diffusivity of the second dopant in silicon; and
a second epitaxial layer disposed on the first epitaxial layer,
the first epitaxial layer including the ion-implanted capping layer having a thickness configured to contain up-diffusion of the first dopant having the higher diffusivity from the silicon wafer in the first epitaxial layer in thermal processes for fabricating the vertical MOSFET device,
the ion-implanted capping layer configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into the second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.
2. The substrate of claim 1 , wherein the silicon wafer is a phosphorus doped n + silicon wafer, the ion-implanted capping layer is an arsenic-implanted buried layer.
3. The substrate of claim 1 , wherein the ion-implanted capping layer is formed by a dose of arsenic ions implanted in the first epitaxial layer at an implant energy.
4. The substrate of claim 3 , wherein the dose is in a range of about 2E13 atoms/cm 2 to 1E16 atoms/cm 2 and the implant energy is in a range of about 60 keV to 100 keV.
5. The substrate of claim 4 , wherein the ion-implanted capping layer is annealed at a temperature in a range of about 950° C. to 1200° C. for an anneal time in a range of about 30 minutes to 240 minutes.
6. The substrate of claim 4 , wherein the annealed ion-implanted capping layer has a peak arsenic dopant concentration in a range of about 1×10 +18 to 5×10 +19 atoms/cc.
7. The substrate of claim 1 , wherein the first epitaxial layer and second epitaxial layer as first grown on silicon wafer have phosphorus dopant concentrations in a range of about 10 +14 to 10 +17 atoms/cc.
8. The substrate of claim 1 , wherein a mesa is formed in the second epitaxial layer, the mesa including a drift region of a MOSFET device formed on the substrate.
9. A vertical MOSFET device, the vertical MOSFET device comprising:
a heavily doped silicon substrate including a drain of the vertical MOSFET device; and
a semiconductor mesa including a drift region of the vertical MOSFET device, the semiconductor mesa disposed on a first epitaxial layer, the first epitaxial layer disposed on the heavily doped silicon substrate, the semiconductor mesa being formed in a second epitaxial layer disposed on the first epitaxial layer,
the first epitaxial layer including an ion-implanted capping layer having a thickness t configured to contain up-diffusion of a first dopant from the heavily doped silicon substrate into the first epitaxial layer in thermal processes for fabricating the vertical MOSFET device,
the ion-implanted capping layer configured to limit up-diffusion of the first dopant from the heavily doped silicon substrate through the ion-implanted capping layer into the semiconductor mesa such that a concentration of the first dopant in the semiconductor mesa is lower than a concentration of the first dopant in the first epitaxial layer.
10. The vertical MOSFET device of claim 9 , wherein the heavily doped silicon substrate is a phosphorus doped n + silicon wafer, and wherein the ion-implanted capping layer is an arsenic-implanted buried layer.
11. The vertical MOSFET device of claim 10 , wherein the ion-implanted capping layer in the vertical MOSFET device has a peak arsenic dopant concentration in a range of about 5×10 +17 to 10 +19 atoms/cm 3 .
12. The vertical MOSFET device of claim 10 , wherein the ion-implanted capping layer is disposed in a first epitaxial layer grown on the phosphorus doped n + silicon wafer.
13. The vertical MOSFET device of claim 9 , wherein the drift region of the vertical MOSFET device included in the semiconductor mesa has phosphorus dopant concentrations in a range of about 1×10 +15 to 3×10 +17 atoms/cm 3 .
14. The vertical MOSFET device of claim 9 , wherein a net dopant concentration profile has a decreasing value from the drain of the vertical MOSFET device to a valley region in the first epitaxial layer, an increasing value from the valley region to a peak value at a peak in the ion-implanted capping layer, and a decreasing value from the peak into the drift region of the vertical MOSFET device.
15. A MOSFET device comprising:
a drain region formed in a phosphorus doped silicon wafer;
an epitaxial layer doped with phosphorus disposed on the phosphorus doped silicon wafer;
a source region formed in a device layer disposed on the epitaxial layer doped with phosphorus; and
an arsenic ion-implanted capping layer implanted in the epitaxial layer below the source region in the device layer and above the drain region formed in the phosphorus doped silicon wafer, the arsenic ion-implanted capping layer limiting up-diffusion of phosphorus dopant from the phosphorus doped silicon wafer through the arsenic ion-implanted capping layer such that a concentration of the phosphorus dopant in the device layer at or above the arsenic ion-implanted capping layer is lower than a concentration of the phosphorus dopant in the epitaxial layer below the arsenic ion-implanted capping layer.
16. The MOSFET device of claim 15 , wherein the arsenic ion-implanted capping layer comprises a thermally annealed arsenic ion implanted layer.
17. The MOSFET device of claim 15 , wherein the arsenic ion-implanted capping layer has a peak arsenic dopant concentration of about 5×10 +17 atoms/cc to 5×10 +19 atoms/cc.
18. The MOSFET device of claim 15 , wherein the arsenic ion-implanted capping layer comprises multiple doses of arsenic ions at multiple implant energies.
19. The MOSFET device of claim 18 , wherein each of the multiple doses of the arsenic ions is implanted in a new epitaxial layer grown after annealing and stripping a screen oxide of a previous arsenic implantation.
20. The MOSFET device of claim 15 , wherein the device layer disposed on the epitaxial layer doped with phosphorus includes another epitaxial layer having phosphorus dopant concentrations in a range of about 10 +15 to 10 +17 atoms/cm 3 .