Structures and methods for source-down vertical semiconductor device
A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.
1. A method of forming a semiconductor device, comprising:
providing a semiconductor wafer having a first side and a second side opposite to the first side and semiconductor devices, wherein each semiconductor device comprises a gate pad and active device structures including source regions and gate electrodes adjacent to the first side, and a drain region and a gate region at the second side, and wherein the gate pad is electrically coupled to the gate electrodes;
providing a conductive structure extending from the gate pad at least partially through the semiconductor wafer towards the second side to electrically couple the gate pad to the gate region at the second side;
providing a first electrode over the first side electrically coupled to the source regions and electrically isolated from the gate pad;
providing a second electrode at the second side adjacent to the gate region and electrically coupled to the conductive structure; and
providing a third electrode electrically coupled to the drain region at the second side.
2. The method of claim 1 , further comprising:
plasma etching the semiconductor wafer from the second side towards the front side while the semiconductor wafer is attached to a carrier substrate to provide first singulation lines; and
removing portions of semiconductor wafer through the first singulation lines to provide second singulation lines to separate the first conductor.
3. The method of claim 2 , wherein:
the removing step comprises sawing.
4. The method of claim 2 , wherein:
the removing step comprises laser processing.
5. The method of claim 2 , wherein:
the first singulation lines are wider than the second singulation lines.
6. The method of claim 5 , wherein:
the plasma etching step and the removing step form a solder dam structure for each semiconductor device.
7. The method of claim 1 , further comprising:
providing an isolation structure, wherein the isolation structure electrically isolates the conductive structure from the source regions and the drain region;
providing a dielectric over the gate pad to electrically isolate the gate pad from the first electrode; and
removing part of the second side using the isolation structure for endpoint detection.
8. The method of claim 1 , wherein:
providing the conductive structure comprises providing through-semiconductor vias comprising a conductive fill material.
9. The method of claim 1 , wherein:
providing the conductive structure comprises providing the conductive structure partially extending through the semiconductor wafer so that a part of the semiconductor wafer is interposed between a proximate end of the conductive structure and the second electrode.
10. The method of claim 1 , wherein:
providing the conductive structure comprises providing the conductive structure extending all the way through the semiconductor wafer; and
a proximate end of the conductive structure directly contacts the third electrode.
11. The method of claim 1 , wherein:
providing the conductive structure comprises providing the conductive structure comprising a dielectric ring surrounding a conductive fill material.