IP Library Granted Patent US 11,837,670
Granted Patent B2
US 11,837,670 · App. 16/949,228 · Granted Dec 5, 2023

Semiconductor devices with single-photon avalanche diodes, light scattering structures, and multiple deep trench isolation structures

Inventors: Marc Allen Sulfridge (Boise, ID); Anne Deignan (County Limerick, IE); Nader Jedidi (Cork, IE); Michael Gerard Keyes (Dromcollogher, IE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L31/02027G02B3/06H01L27/1463H01L27/14605H01L27/14621H01L27/14627H01L27/14629H01L27/14643H01L27/14649H01L31/02327H01L31/055H01L31/107H01L27/1464H04N25/63
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,837,670
App. No.
16/949,228
Granted
Dec 5, 2023
Kind
B2
Abstract

An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, multiple rings of isolation structures may be formed around the SPAD. An outer deep trench isolation structure may include a metal filler such as tungsten and may be configured to absorb light. The outer deep trench isolation structure therefore prevents crosstalk between adjacent SPADs. Additionally, one or more inner deep trench isolation structures may be included. The inner deep trench isolation structures may include a low-index filler to reflect light and keep incident light in the active area of the SPAD.

Claims (34)

1. A semiconductor device comprising:

a substrate having a thickness;

a single-photon avalanche diode in the substrate;

a first deep trench isolation structure in the substrate that forms a first ring around the single-photon avalanche diode; and

a second deep trench isolation structure in the substrate that forms a second ring around the single-photon avalanche diode, wherein the second deep trench isolation structure has a depth that is less than the thickness.

2. The semiconductor device defined in claim 1 , wherein the first deep trench isolation structure comprises a trench and a metal filler in the trench.

3. The semiconductor device defined in claim 2 , wherein the metal filler comprises tungsten.

4. A semiconductor device comprising:

a substrate having a thickness;

a single-photon avalanche diode in the substrate;

a first deep trench isolation structure in the substrate that forms a first ring around the single-photon avalanche diode; and

a second deep trench isolation structure in the substrate that forms a second ring around the single-photon avalanche diode, wherein the second deep trench isolation structure has a depth that is less than the thickness, wherein the first deep trench isolation structure comprises a trench and a metal filler in the trench, and wherein the metal filler is coupled to a bias voltage and serves as an anode contact for the single-photon avalanche diode.

5. The semiconductor device defined in claim 1 , wherein the first deep trench isolation structure comprises a trench and a light absorbing filler in the trench.

6. The semiconductor device defined in claim 5 , wherein the second deep trench isolation structure comprises an additional trench and a low-index filler in the additional trench.

7. The semiconductor device defined in claim 1 , wherein the second deep trench isolation structure is interposed between the first deep trench isolation structure and the single-photon avalanche diode.

8. The semiconductor device defined in claim 7 , wherein the first deep trench isolation structure is configured to absorb light and wherein the second deep trench isolation structure is configured to reflect light.

9. The semiconductor device defined in claim 7 , wherein the first deep trench isolation structure is a front side deep trench isolation structure and wherein the second deep trench isolation structure is a backside deep trench isolation structure.

10. The semiconductor device defined in claim 1 , further comprising:

a plurality of light scattering structures in the substrate over the single-photon avalanche diode.

11. The semiconductor device defined in claim 1 , wherein the second deep trench isolation structure comprises a trench in the substrate and a p-type doped liner adjacent to the trench.

12. The semiconductor device defined in claim 11 , wherein the p-type doped liner is coupled to a bias voltage and serves as an anode contact for the single-photon avalanche diode.

13. A semiconductor device comprising:

a substrate;

a single-photon avalanche diode in the substrate;

an outer ring-shaped deep trench isolation structure having a central opening, wherein the single-photon avalanche diode is in the central opening; and

an inner ring-shaped deep trench isolation structure that surrounds the single-photon avalanche diode and that is in the central opening, wherein the inner ring-shaped deep trench isolation structure is interposed between the single-photon avalanche diode and the outer ring-shaped deep trench isolation structure and wherein the inner ring-shaped deep trench isolation structure is more reflective than the outer ring-shaped deep trench isolation structure.

14. The semiconductor device defined in claim 1 , wherein the first deep trench isolation structure forms the first ring around the single-photon avalanche diode within a given plane, wherein the second deep trench isolation structure forms the second ring around the single-photon avalanche diode within the given plane, wherein the second deep trench isolation structure is interposed between the first deep trench isolation structure and the single-photon avalanche diode within the given plane, wherein the first deep trench isolation structure extends completely through the thickness of the substrate, wherein the first deep trench isolation structure comprises a first trench and a first filler in the first trench, wherein the second deep trench isolation structure comprises a second trench and a second filler in the second trench, and wherein the second filler is more reflective than the first filler.

15. The semiconductor device defined in claim 13 , wherein the substrate has a thickness, wherein the outer ring-shaped deep trench isolation structure extends completely through the thickness of the substrate, and wherein the inner ring-shaped deep trench isolation structure has a depth that is less than the thickness.

16. The semiconductor device defined in claim 4 , wherein the first deep trench isolation structure extends completely through the thickness of the substrate.

17. The semiconductor device defined in claim 4 , wherein the second deep trench isolation structure extends only partially through the thickness of the substrate.

18. The semiconductor device defined in claim 13 , wherein the outer ring-shaped deep trench isolation structure comprises a trench and a metal filler in the trench and wherein the metal filler is coupled to a bias voltage and serves as an anode contact for the single-photon avalanche diode.

19. The semiconductor device defined in claim 13 , wherein the inner ring-shaped deep trench isolation structure comprises a trench in the substrate and a p-type doped liner adjacent to the trench and wherein the p-type doped liner is coupled to a bias voltage and serves as an anode contact for the single-photon avalanche diode.

20. The semiconductor device defined in claim 15 , wherein the substrate has first and second opposing sides and wherein the semiconductor device further comprises:

a plurality of light scattering structures in the first side of the substrate over the single-photon avalanche diode, wherein the inner ring-shaped deep trench isolation structure extends from the second side of the substrate towards the first side of the substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2020
From: SULFRIDGE, MARC ALLEN; DEIGNAN, ANNE; JEDIDI, NADER; KEYES, MICHAEL GERARD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054123/0790 →
Continuity (3)
Provisional Application 62981902 · Feb 26, 2020
Provisional Application 62943475 · Dec 4, 2019
Related Publication 20210175265A1 · Jun 10, 2021
Cited By (1)
US 12,199,198