IP Library Granted Patent US 11,438,574
Granted Patent B2
US 11,438,574 · App. 16/949,324 · Granted Sep 6, 2022

Stitched integrated circuit dies

Inventors: Nicholas Paul Cowley (Wroughton, GB); Andrew David Talbot (Chieveley, GB)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N17/002H04N5/379H04N5/37452H01L27/14603
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Quick Facts
Patent No.
US 11,438,574
App. No.
16/949,324
Granted
Sep 6, 2022
Kind
B2
Abstract

An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Claims (34)

1. An image sensor die comprising:

a plurality of circuitry block instantiations of a same circuitry block;

multiplexer circuitry coupled to each of the plurality of circuitry block instantiations;

a circuit coupled to the plurality of circuitry block instantiations using the multiplexer circuitry, wherein any one of the plurality of circuitry block instantiations is configurable to control the circuit;

memory circuitry configured to store information indicative of a functional circuitry block instantiation in the plurality of circuitry block instantiations; and

control circuitry coupled to the plurality of circuitry block instantiations, the multiplexer circuitry, and the memory circuitry, wherein the control circuitry is configured to enable the functional circuitry block instantiation based on the information stored at the memory circuitry and is configured to control the multiplexer circuitry to connect the functional circuitry block instantiation to the circuit.

2. The image sensor die defined in claim 1 , wherein the control circuitry is configured to receive a test signal from test circuitry to test a given one of the plurality of circuitry block instantiations.

3. The image sensor die defined in claim 2 , wherein the multiplexer circuitry is configured to couple the given circuitry block instantiation to the test circuitry.

4. The image sensor die defined in claim 3 , wherein, in response to the given circuitry block instantiation passing the test, information indicative of the given circuitry block instantiation is stored at the memory circuitry as the information indicative of the functional circuitry block instantiation.

5. The image sensor die defined in claim 4 , wherein the information indicative of the functional circuitry block instantiation comprises a location of the functional circuitry block instantiation on the image sensor die.

6. The image sensor die defined in claim 1 , wherein the image sensor die is a stitched image sensor die formed from stitching tiles in a same reticle set.

7. The image sensor die defined in claim 6 , further comprising:

image sensor pixel circuitry formed from one or more instantiations of a pixel tile in the reticle set.

8. The image sensor die defined in claim 7 , wherein each of the plurality of circuitry block instantiations is formed from a corresponding instantiation of a peripheral circuitry tile in the reticle set.

9. The image sensor die defined in claim 1 , wherein the memory circuitry comprises on-die programmable memory, and the control circuitry is configured to receive, from the on-die programmable memory, the stored information indicative of the functional circuitry block instantiation during a device initialization operation.

10. The image sensor die defined in claim 9 , wherein, during the device initialization operation, the control circuitry is configured to enable the functional circuitry block instantiation and control the multiplexer circuitry to connect the functional circuitry block to the circuit.

11. A stitched integrated circuit die comprising:

a plurality of circuitry block instantiations formed from a same physical tile in a reticle set;

multiplexer circuitry coupled to each of the plurality of circuitry block instantiations using corresponding paths;

a circuit coupled to a selected one of the plurality of circuitry block instantiations via the multiplexer circuitry, wherein the circuit is configured to be controlled by any one of the plurality of circuitry block instantiations;

memory circuitry configured to store information indicative of the selected circuitry block instantiation, the selected circuitry block instantiation being identified as a functional circuitry block instantiation in the plurality of circuitry block instantiations; and

control circuitry coupled to the plurality of circuitry block instantiations, the multiplexer circuitry, and the memory circuitry, wherein the control circuitry is configured to enable the selected circuitry block instantiation and control the multiplexer circuitry to couple the selected circuitry block instantiation to the circuit based on the information stored at the memory circuitry.

12. The stitched integrated circuit die defined in claim 11 , wherein the multiplexer circuitry is configured to couple the selected circuitry block instantiation to test circuitry to determine whether the selected circuitry block instantiation is functional.

13. The stitched integrated circuit die defined in claim 12 , wherein the control circuitry is configured to receive a test signal from the test circuitry to perform a test on the selected circuitry block instantiation.

14. The stitched integrated circuit die defined in claim 11 , wherein the stitched integrated circuit die is a stitched image sensor integrated circuit die.

15. The image sensor die defined in claim 1 , wherein the control circuitry is configured to control the multiplexer circuitry to disconnect a remaining portion of the plurality of circuitry block instantiations other than the functional circuitry block instantiation.

16. The image sensor die defined in claim 1 , wherein the control circuitry is configured to disable at least one of the plurality of circuitry block instantiations other than the functional circuitry block instantiation.

17. The image sensor die defined in claim 16 , wherein the control circuitry is configured to disable the one of the plurality of circuitry block instantiations in response to information indicating the one of the plurality of circuitry block instantiations being faulty.

18. A method of forming an image sensor die, the method comprising:

forming a plurality of circuitry block instantiations of a same circuitry block;

coupling multiplexer circuitry to each of the plurality of circuitry block instantiations;

using the multiplexer circuitry to couple a circuit to the plurality of circuitry block instantiations, wherein any one of the plurality of circuitry block instantiations is configurable to control the circuit;

forming memory circuitry configured to store information indicative of a functional circuitry block instantiation in the plurality of circuitry block instantiations; and

coupling control circuitry to the plurality of circuitry block instantiations, the multiplexer circuitry, and the memory circuitry, wherein the control circuitry is configured to enable the functional circuitry block instantiation based on the information stored at the memory circuitry and is configured to control the multiplexer circuitry to connect the functional circuitry block instantiation to the circuit.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2020
From: COWLEY, NICHOLAS PAUL; TALBOT, ANDREW DAVID
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054166/0751 →