IP Library Granted Patent US 11,387,145
Granted Patent B2
US 11,387,145 · App. 16/950,097 · Granted Jul 12, 2022

Jet ablation die singulation systems and related methods

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/78H01L21/3046H01L21/3065H01L21/561H01L23/3171
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Quick Facts
Patent No.
US 11,387,145
App. No.
16/950,097
Granted
Jul 12, 2022
Kind
B2
Abstract

Implementations of a method of singulating a plurality of semiconductor die may include forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate; etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.

Claims (30)

1. A method of singulating a plurality of semiconductor die, the method comprising:

forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate;

etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and

jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.

2. The method of claim 1 , wherein forming an opening in the layer of passivation material further comprises one of etching or jet ablating.

3. The method of claim 1 , wherein jet ablating one or more portions of the layer of passivation material further comprises jet ablating from the second side of the semiconductor substrate.

4. The method of claim 1 , wherein jet ablating one or more portions of the layer of passivation material further comprises jet ablating from the first side of the semiconductor substrate.

5. The method of claim 1 , wherein etching substantially through the thickness of the semiconductor substrate further comprises plasma etching.

6. The method of claim 1 , wherein the thickness of the semiconductor substrate is less than 50 microns.

7. The method of claim 1 , wherein the thickness of the semiconductor substrate is 25 microns.

8. The method of claim 1 , further comprising jet ablating one or more portions of the layer of passivation material after etching substantially through the thickness of the semiconductor substrate.

9. A method of singulating a plurality of semiconductor die, the method comprising:

forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate, the semiconductor substrate comprising a plurality of semiconductor die;

etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer to form a plurality of sidewalls across the thickness;

etching substantially through a thickness of a passivation layer coupled to a second side of the semiconductor substrate at the pattern in the back metal layer to form an opening in the passivation layer; and

jet ablating one or more portions of the passivation layer overhanging the plurality of sidewalls.

10. The method of claim 9 , wherein jet ablating one or more portions of the passivation layer further comprises jet ablating from the second side of the semiconductor substrate.

11. The method of claim 9 , wherein jet ablating one or more portions of the passivation layer further comprises jet ablating from the first side of the semiconductor substrate.

12. The method of claim 9 , wherein etching substantially through the thickness of the semiconductor substrate further comprises plasma etching.

13. The method of claim 9 , wherein the thickness of the semiconductor substrate is less than 50 microns.

14. The method of claim 9 , wherein the thickness of the semiconductor substrate is 25 microns.

15. The method of claim 9 , further comprising jet ablating one or more portions of the passivation layer after forming the opening in the passivation layer.

16. A method of singulating a plurality of semiconductor die, the method comprising:

mounting a semiconductor substrate to a tape;

etching substantially through a thickness of the semiconductor substrate at a plurality of die streets to form etched sidewalls along the thickness; and

jet ablating one or more portions of a layer of passivation material that overhangs the etched sidewalls;

wherein the layer of passivation material is used as a mask for etching substantially through the thickness of the semiconductor substrate.

17. The method of claim 16 , wherein etching substantially through the thickness further comprises plasma etching.

18. The method of claim 16 , wherein jet ablating one or more portions of the layer of passivation material further comprises jet ablating from a second side of the semiconductor substrate.

19. The method of claim 16 , wherein jet ablating one or more portions of the layer of passivation material further comprises jet ablating from a first side of the semiconductor substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2022
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 059218/0454 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →