Semiconductor devices and manufacturing methods thereof
A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
1. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate;
a gate electrode surrounding the plurality of channel layers; and
source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer and a second epitaxial layer on the first epitaxial layer,
wherein the second epitaxial layer is in a center region of each of the source/drain structures,
wherein the first epitaxial layer surrounds a bottom surface and both side surfaces of the second epitaxial layer, and
wherein the side surfaces of the second epitaxial layer each comprise first portions that are inclined so that a width of the second epitaxial layer decreases toward the substrate.
2. The semiconductor device of claim 1 , wherein the side surfaces of the second epitaxial layer further comprise:
second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions; and
third portions that are curved from lower ends of the first portions.
3. The semiconductor device of claim 2 , wherein a first width of the second epitaxial layer between the second portions is greater than a second width of the first epitaxial layer contacting the first portions of the second epitaxial layer.
4. The semiconductor device of claim 2 , wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures.
5. The semiconductor device of claim 2 , wherein a surface of the first epitaxial layer contacting the second portion of the side surfaces of the second epitaxial layer comprises a curved portion.
6. The semiconductor device of claim 1 , wherein the second epitaxial layer covers a portion of an upper surface of the first epitaxial layer.
7. The semiconductor device of claim 1 , wherein an upper surface of the second epitaxial layer comprises a recessed portion.
8. The semiconductor device of claim 1 , wherein the first epitaxial layer and the second epitaxial layer each comprise silicon germanium, and
wherein a germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.
9. The semiconductor device of claim 1 , wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has an inclined lateral surface.
10. The semiconductor device of claim 1 , wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has a length extending in a first direction that decreases toward the substrate.
11. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate;
a gate electrode surrounding the plurality of channel layers, the gate electrode extending in a first direction;
source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer; and
a plurality of spacers on side surfaces of the gate electrode, the plurality of spacers being in contact with the third epitaxial layer,
wherein the first epitaxial layer covers surrounds a bottom surface and side surfaces of the second epitaxial layer,
wherein at least one of the source/drain structures comprises an upper portion having a convex shape protruding upwardly to a level higher than an upper surface of an uppermost channel layer among the plurality of channel layers,
wherein the at least one of the source/drain structures comprises a middle portion below the upper portion, and
wherein a width of the upper portion in a second direction perpendicular to the first direction is smaller than a width of the middle portion in the second direction.
12. The semiconductor device of claim 11 , wherein the first epitaxial layer includes 17 at % to 27 at % Germanium (Ge), the second epitaxial layer includes 37 at % to 47 at % Ge, and the third epitaxial layer includes 50 at % to 60 at % Ge.
13. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate;
a gate electrode surrounding the plurality of channel layers; and
source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer and a second epitaxial layer having different compositions from each other,
wherein the second epitaxial layer covers a portion of an upper surface of the first epitaxial layer,
wherein side surfaces of the second epitaxial layer each comprise first portions having a slope with respect to an upper surface of the substrate; and
wherein the side surfaces of the second epitaxial layer further comprise:
second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions; and
third portions curved from lower ends of the first portions.
14. The semiconductor device of claim 13 , wherein a first width of the second epitaxial layer between the second portions is greater than a second width of the first epitaxial layer contacting the first portions of the second epitaxial layer.
15. The semiconductor device of claim 13 , wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures.
16. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate;
a gate electrode surrounding the plurality of channel layers; and
source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer and a second epitaxial layer having different compositions from each other,
wherein the second epitaxial layer is in a center region of each of the source/drain structures,
wherein the first epitaxial layer surrounds a bottom surface and both side surfaces of the second epitaxial layer, and
wherein the side surfaces of the second epitaxial layer each comprise first portions that are inclined so that a width of the second epitaxial layer decreases toward the substrate and second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions.
17. The semiconductor device of claim 16 , wherein a first width of the second epitaxial layer between the second portions is greater than a second width of the first epitaxial layer contacting the first portions of the second epitaxial layer.
18. The semiconductor device of claim 16 , wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures.
19. The semiconductor device of claim 16 , wherein a surface of the first epitaxial layer contacting the second portion of the side surfaces of the second epitaxial layer comprises a curved portion.
20. The semiconductor device of claim 16 , wherein an upper surface of the second epitaxial layer comprises a recessed portion.