Semiconductor devices and manufacturing methods thereof
A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
1. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate, the plurality of channel layers comprising a first channel layer and a second channel layer;
a gate electrode surrounding the plurality of channel layers; and
embedded source/drain layers on opposing sides of the gate electrode, the embedded source/drain layers each having a first region and a second region that is on the first region, the second region comprising a plurality of layers having different compositions,
wherein lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are inclined with respect to an upper surface of the substrate.
2. The semiconductor device of claim 1 , further comprising:
interfacial layers comprising first portions that are between the embedded source/drain layers and the plurality of channel layers and comprising a second portion that is between the embedded source/drain layers and the substrate,
wherein a first composition of the first region is different from a second composition of at least one of the interfacial layers, and
wherein each of the first portions and the second portion are spaced apart from each other in a direction perpendicular to the upper surface of the substrate.
3. The semiconductor device of claim 2 , wherein the first region and the plurality of channel layers both comprise a first semiconductor material, and
wherein the interfacial layers and the second region both comprise a second semiconductor material.
4. The semiconductor device of claim 1 , wherein the first region further comprises p-type impurities.
5. The semiconductor device of claim 1 , wherein the second region comprises a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially stacked on the first region.
6. The semiconductor device of claim 5 , wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer comprise a silicon germanium compound,
wherein a third germanium content of the third epitaxial layer is higher than a second germanium content of the second epitaxial layer, and
wherein the second germanium content of the second epitaxial layer is higher than a first germanium content of the first epitaxial layer.
7. The semiconductor device of claim 1 , wherein a length of at least a region of the second channel layer is greater than a length of the first channel layer.
8. The semiconductor device of claim 1 , wherein the lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are flat surfaces that are inclined with respect to the upper surface of the substrate.
9. The semiconductor device of claim 1 , wherein the lateral surfaces of the second channel layer adjacent to the embedded source/drain layers are curved surfaces that are inclined with respect to the upper surface of the substrate.
10. The semiconductor device of claim 1 , wherein a length of an upper portion of the second channel layer is greater than a length of a lower portion of the second channel layer.
11. The semiconductor device of claim 1 , wherein the plurality of channel layers further comprise a third channel layer,
wherein the third channel layer has a length decreasing toward the substrate, and
wherein the first channel layer has a length increasing toward the substrate.
12. The semiconductor device of claim 1 , wherein respective ones of the plurality of channel layers have a thickness in a first direction perpendicular to the substrate that is less than a width in a second direction crossing the first direction.
13. A semiconductor device, comprising:
a substrate;
a plurality of channel layers stacked on the substrate, the plurality of channel layers extending in a first direction;
a gate electrode surrounding the plurality of channel layers, the gate electrode extending in a second direction, intersecting the first direction; and
embedded source/drain layers on opposing sides of the gate electrode,
wherein at least one first channel layer of the plurality of channel layers has a region having a first length extending farther in the first direction than a second length of a second channel layer of the plurality of channel layers that is adjacent to the first channel layer,
wherein the embedded source/drain layers each have a first region and a second region that is on the first region, and
wherein the second region comprises a plurality of layers having different compositions.
14. The semiconductor device of claim 13 , wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has an inclined lateral surface.
15. The semiconductor device of claim 13 , wherein a top channel layer of the plurality of channel layers that is farthest from the substrate has a length extending in the first direction that decreases toward the substrate.
16. The semiconductor device of claim 13 , further comprising:
interfacial layers between the embedded source/drain layers and the plurality of channel layers and between the embedded source/drain layers and the substrate.