Silicon carbide semiconductor device
View Patent ↗A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
a gate pad facing the first main surface; and
a drain electrode in contact with the second main surface,
the silicon carbide substrate including
a first impurity region constituting the second main surface and having a first conductivity type,
a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type,
a third impurity region provided on the second impurity region and having the first conductivity type, and
a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type,
each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region being located between the gate pad and the drain electrode,
when viewed from a direction perpendicular to the first main surface, an outer edge of the second impurity region surrounds an outer edge of the gate pad.
2. The silicon carbide semiconductor device according to claim 1 , further comprising a source electrode located on the first main surface, wherein
the second impurity region is electrically connected with the source electrode.
3. The silicon carbide semiconductor device according to claim 1 , wherein the second impurity region has an impurity concentration of more than or equal to 1×10 17 cm −3 and less than or equal to 1×10 20 cm −3 .
4. The silicon carbide semiconductor device according to claim 1 , wherein the second impurity region has a thickness of more than or equal to 100 nm and less than or equal to 2 μm.
5. The silicon carbide semiconductor device according to claim 1 , wherein the fourth impurity region has an impurity concentration of more than or equal to 1×10 16 cm −3 and less than or equal to 1×10 20 cm −3 .
6. The silicon carbide semiconductor device according to claim 1 , wherein the fourth impurity region has a thickness of more than or equal to 100 nm and less than or equal to 2 μm.
7. The silicon carbide semiconductor device according to claim 1 , wherein, when viewed from a direction perpendicular to the first main surface, an area of the second impurity region is more than or equal to an area of the gate pad.
8. The silicon carbide semiconductor device according to claim 1 , wherein, when viewed from a direction perpendicular to the first main surface, an area of the fourth impurity region is more than or equal to an area of the gate pad.
9. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
a gate pad facing the first main surface;
a drain electrode in contact with the second main surface; and
a source electrode located on the first main surface,
the silicon carbide substrate including
a first impurity region constituting the second main surface and having a first conductivity type,
a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type,
a third impurity region provided on the second impurity region and having the first conductivity type, and
a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type,
each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region being located between the gate pad and the drain electrode,
the second impurity region being electrically connected with the source electrode,
when viewed from a direction perpendicular to the first main surface, an area of each of the second impurity region and the fourth impurity region being more than or equal to an area of the gate pad,
when viewed from a direction perpendicular to the first main surface, an outer edge of the second impurity region surrounds an outer edge of the gate pad.
10. The silicon carbide semiconductor device according to claim 9 , wherein the second impurity region has an impurity concentration of more than or equal to 1×10 17 cm −3 and less than or equal to 1×10 20 cm −3 .
11. The silicon carbide semiconductor device according to claim 9 , wherein the second impurity region has a thickness of more than or equal to 100 nm and less than or equal to 2 μm.
12. The silicon carbide semiconductor device according to claim 9 , wherein the fourth impurity region has an impurity concentration of more than or equal to 1×10 16 cm −3 and less than or equal to 1×10 20 cm −3 .
13. The silicon carbide semiconductor device according to claim 9 , wherein the fourth impurity region has a thickness of more than or equal to 100 nm and less than or equal to 2 μm.