Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate functioning as a channel of a cell transistor; a first silicon nitride layer above the semiconductor having an internal compressive stress of a first value; and a second silicon nitride layer above the first silicon nitride layer having an internal compressive stress of a second value. The second value is greater than the first value.
1. A semiconductor memory device comprising:
a substrate;
a semiconductor above the substrate, the semiconductor functioning as a channel of a cell transistor;
a first silicon nitride layer above the semiconductor, the first silicon nitride layer having an internal compressive stress of a first value; and
a second silicon nitride layer above the first silicon nitride laver; the second silicon nitride layer having an internal compressive stress of a second value, the second value being greater than the first value, wherein
the first silicon nitride layer has an amount of N—H couplings of a third value,
the second silicon nitride layer has an amount of N—H couplings of a fourth value, and,
the fourth value is greater than the third value.
2. The device according to claim 1 , wherein
the first silicon nitride layer has a density of a fifth value,
the second silicon nitride layer has a density of a sixth value, and
the sixth value is greater than the fifth value.
3. The device according to claim 1 , wherein
the second silicon nitride layer is located on a surface of the semiconductor memory device.
4. The device according to claim 1 , wherein
the first silicon nitride layer has an amount of Si—H couplings of a seventh value,
the second silicon nitride layer has an amount of Si—H couplings of an eighth value, and
the eighth value is smaller than the seventh value.