IP Library Granted Patent US 11,482,489
Granted Patent B2
US 11,482,489 · App. 16/990,793 · Granted Oct 25, 2022

Semiconductor device and method of manufacturing the same

Inventors: Shingo Nakajima (Yokkaichi, JP); Ryota Asada (Kuwana, JP); Hidenobu Nagashima (Yokkaichi, JP); Masayuki Akou (Yokkaichi, JP)
Assignee: KIOXIA CORPORATION
H01L23/5226H01L23/535H01L23/53295H01L27/11556H01L27/11582
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Quick Facts
Patent No.
US 11,482,489
App. No.
16/990,793
Granted
Oct 25, 2022
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.

Claims (21)

1. A semiconductor device comprising:

a substrate;

a transistor provided on the substrate;

a first interconnect layer provided above the transistor and electrically coupled to the transistor;

a first conductive layer provided above the first interconnect layer;

a layer stack provided above the first interconnect layer, the layer stack comprising a plurality of second conductive layers separated from each other;

a pillar extending through the layer stack in a first direction and including a semiconductor layer, the first direction being a stacking direction of the second conductive layers the semiconductor layer electrically coupled to the first conductive layer, an end of the pillar being in contact with the first interconnect layers;

a first silicon nitride layer provided between the first interconnect layer and the first conductive layer; and

a first contact that extends in the layer stack and in the first silicon nitride layer in a stacking direction of the layer stack and is electrically coupled to the first interconnect, wherein

the first contact comprises:

a first metal layer continuously extending in the layer stack and in the first silicon nitride layer in the stacking direction;

a second silicon nitride layer provided between the first metal layer and the layer stack and between the first metal layer and the first silicon nitride layer; and

a first silicon oxide layer provided between the second silicon nitride layer and the layer stack.

2. The device according to claim 1 , wherein the first contact further comprises a third silicon nitride layer provided on the first metal layer.

3. The device according to claim 1 , further comprising a second silicon oxide layer provided above the layer stack and containing impurities,

wherein:

the first metal layer continuously extends in the second silicon oxide layer, in the layer stack, and in the first silicon nitride layer in the stacking direction, and

the second silicon nitride layer is provided between the first metal layer and the second silicon oxide layer.

4. The device according to claim 3 , wherein the impurities comprise at least one of phosphorus, carbon, arsenic, or argon.

5. The device according to claim 1 , further comprising a fourth silicon nitride layer provided around the layer stack,

wherein a lower end of the fourth silicon nitride layer is connected to the first silicon nitride layer.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058785/0124 →
CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058785/0197 →