Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array

1. A method of manufacturing a single poly non-volatile memory device, the method comprising:

forming a first type lower well by doping first type impurities in a semiconductor substrate;

forming first and second wells separated in an upper portion of the first type lower well by doping same type impurities;

forming a first type well to enclose the first and second wells by doping impurities having a conductivity type different than that of the first and second wells; and

forming a selection transistor and a sensing transistor on an upper portion of the first well and simultaneously forming a control gate on an upper portion of the second well separated on an opposite side of a source electrode from the first well.

2. The method of claim 1 , wherein the selection transistor and the sensing transistor are formed on the first well and comprise a gate of the selection transistor and a gate of the sensing transistor.

3. The method of claim 2 , wherein the control gate and the gate of the sensing transistor are connected through a floating gate.

4. The method of claim 1 , further comprising forming a doping layer that shares a drain area of the selection transistor and a source area of the sensing transistor.

5. The method of claim 1 , further comprising forming a first insulating layer between the first well and the second well,

wherein the first type well is further disposed below the first insulating layer formed between the first well and the second well.

6. The method of claim 5 , wherein the first insulating layer is disposed below the floating gate.

7. The method of claim 1 , further comprising:

forming an implant area at an upper portion of the second well to be disposed parallel to or wider than the control gate at a lower end of the control gate; and

forming a second insulating layer between the control gate and the implant area.

8. The method of claim 1 , further comprising forming a first diffusion area and a second diffusion area in the first well and the second well, respectively,

wherein the first and second diffusion areas have a same conductivity type.

9. The method of claim 8 , wherein a control gate electrode is connected to the second diffusion area,

wherein a positive program voltage and a negative program voltage are applied to the control gate electrode and the source electrode, respectively, for a program operation, such that electrons are injected into the sensing transistor according to a voltage difference between the control gate electrode and the source electrode.

10. The method of claim 8 , further comprising forming a source area of the selection transistor in the first well, such that the source electrode is connected to both the source area of the selection transistor and the first diffusion area disposed in the first well.

11. The method of claim 1 , further comprising:

forming a drain area of the sensing transistor; and

forming a drain electrode of the sensing transistor connected to the drain area of the sensing transistor.

12. A method of manufacturing a single poly non-volatile memory device, the method comprising:

forming a first type lower well by doping first type impurities in a semiconductor substrate formed by doping second type impurities different from the first type impurities;

forming a first insulating layer in the semiconductor substrate;

forming first well and second well in the first type lower well by doping same type impurities, wherein the first insulating layer is disposed between the first well and the second well;

forming a first type well between the first well and the second well by doping impurities having a conductivity type different than that of the first well and the second well;

forming a selection transistor and a sensing transistor on the first well; and

forming a control gate on the second well,

wherein the control gate is connected to a gate of the sensing transistor via a floating gate formed on the first insulating layer.

13. The method of claim 12 , wherein the first insulating layer is formed with shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

14. The method of claim 13 , wherein the floating gate is formed on the shallow trench isolation (STI).

15. The method of claim 12 , further comprising forming a doping layer in the first well to share a drain area of the selection transistor and a source area of the sensing transistor.

16. The method of claim 12 , wherein the first type well is further disposed below the first insulating layer formed between the first well and the second well.

17. The method of claim 12 , wherein the first type lower well encloses the first well, the second well, the first type well and the first insulating layer.

18. The method of claim 12 , further comprising:

forming an implant area at an upper portion of the second well to be disposed parallel to or wider than the control gate at a lower end of the control gate; and

forming a second insulating layer between the control gate and the implant area.

19. The method of claim 12 , further comprising:

forming a first diffusion area and a second diffusion area in the first well and the second well, respectively, wherein the first and second diffusion areas have a same conductivity type; and

forming a source area of the selection transistor in the first well, such that a source electrode is connected to both the source area of the selection transistor and the first diffusion area disposed in the first well.

20. The method of claim 19 , wherein a control gate electrode is connected to the second diffusion area,

wherein a positive program voltage and a negative program voltage are applied to the control gate electrode and the source electrode, respectively, for a program operation, such that electrons are injected into the sensing transistor according to a voltage difference between the control gate electrode and the source electrode.