Computational storage systems and methods
Example computational storage systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem to process multiple commands. Multiple versatile processing arrays are coupled to the non-volatile memory subsystem. The multiple versatile processing arrays can process multiple in-situ tasks. A host direct memory access module provides direct access to at least one memory device.
1. A storage drive controller comprising:
a non-volatile memory subsystem configured to process a plurality of commands with respect to a non-volatile storage device;
a plurality of versatile processing array slices coupled to the non-volatile memory subsystem, wherein the plurality of versatile processing array slices are configured to receive configuration commands programming the plurality of versatile processing array slices to perform a plurality of in-situ computation tasks; and
a host direct memory access module configured to provide direct access to at least one host memory device, the host direct memory access module configured to:
read data from the at least one host memory device; and
submit the data to the plurality of versatile processing array slices to perform the plurality of in-situ computation tasks.
2. The storage drive controller of claim 1 , wherein the storage drive controller is a solid-state drive controller.
3. The storage drive controller of claim 1 , wherein the plurality of versatile processing array slices are arranged to form a 3-dimensional versatile processing array.
4. The storage drive controller of claim 1 , wherein the plurality of versatile processing array slices are coupled to an interconnect that allows the plurality of versatile processing array slices to communicate with one another.
5. The storage drive controller of claim 1 , wherein each of the plurality of versatile processing array (VPA) slices includes:
a central processing unit;
a (VPA) memory device;
a dynamic configure interface; and
a field-programmable gate array/digital signal processing array.
6. The storage drive controller of claim 5 , wherein the central processing unit includes:
a master interface;
a central processing unit extension instruction interface; and
a peripheral interface.
7. The storage drive controller of claim 5 , wherein the dynamic configure interface includes a direct memory access engine.
8. The storage drive controller of claim 1 , further comprising a buffer management unit (BMU) coupled to the plurality of versatile processing array slices and coupled to a BMU memory device.
9. The storage drive controller of claim 1 , wherein the storage drive controller is configured to process non-volatile memory commands and vendor unique processing commands simultaneously.
10. The storage drive controller of claim 1 , wherein each of the plurality of versatile processing array slices is configured to perform a specific task.
11. The storage drive controller of claim 1 , wherein the non-volatile memory subsystem includes:
a plurality of central processing units; and
a message channel coupled to each of the plurality of central processing units, wherein the message channel allows the plurality of central processing units to communicate with one another.
12. A storage drive controller comprising:
a non-volatile memory subsystem configured to process a plurality of commands with respect to a non-volatile storage device;
a plurality of versatile processing array slices coupled to the non-volatile memory subsystem, wherein the plurality of versatile processing array slices are configured to receive configuration commands programming the plurality of versatile processing array slices to perform a plurality of in-situ computation tasks;
wherein the plurality of versatile processing array slices are arranged to form a 3-dimensional versatile processing array; and
a host direct memory access module configured to provide direct access to at least one host memory device, the host direct memory access module configured to:
read data from the at least one host memory device; and
submit the data to the plurality of versatile processing array slices to perform the plurality of in-situ computation tasks.
13. The storage drive controller of claim 12 , wherein each of the plurality of versatile processing array (VPA) slices includes:
a central processing unit;
a VPA memory device;
a dynamic configure interface; and
a field-programmable gate array/digital signal processing array.
14. The storage drive controller of claim 13 , wherein the central processing unit includes:
a master interface;
a central processing unit extension instruction interface; and
a peripheral interface.
15. The storage drive controller of claim 13 , wherein the dynamic configure interface includes a direct memory access engine.
16. The storage drive controller of claim 12 , wherein the storage drive controller is configured to process non-volatile memory commands and vendor unique processing commands simultaneously.
17. The storage drive controller of claim 12 , wherein the plurality of versatile processing array slices are coupled to an interconnect that allows the plurality of versatile processing array slices to communicate with one another.