IP Library › Granted Patent US 11,694,987
Granted Patent B2
US 11,694,987 · App. 16/999,878 · Granted Jul 4, 2023

Active package substrate having anisotropic conductive layer

Inventors: Juan Eduardo Dominguez (Gilbert, AZ); Hyoung Il Kim (Folsom, CA)
Assignee: Intel Corporation
H01L24/29H01L21/56H01L23/3121H01L23/49827H01L23/49833H01L23/5389H01L24/05H01L24/27H01L24/83H01L25/18H01L24/13H01L2224/04026H01L2224/04105H01L2224/83851
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,694,987
App. No.
16/999,878
Granted
Jul 4, 2023
Kind
B2
Abstract

Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.

Claims (46)

1. A package substrate, comprising:

a bottom substrate layer,

a die mounted on the bottom substrate layer, wherein the die includes a die pad, the die pad embedded in the die;

a top substrate layer over the die, wherein the top substrate layer includes a via; and

an anisotropic conductive layer between the die pad and the via, the anisotropic conductive layer in direct physical contact with the die pad, wherein the via is electrically connected to the die pad through the anisotropic conductive layer.

2. The package substrate of claim 1 , wherein the anisotropic conductive layer includes an anisotropic conductive adhesive, and wherein the anisotropic conductive adhesive conducts electrical current unidirectionally along a vertical axis between the via and the die pad.

3. The package substrate of claim 2 further comprising an epoxy layer surrounding the die between the top substrate layer and the bottom substrate layer.

4. The package substrate of claim 3 further comprising a bottom anisotropic conductive layer between the die and the bottom substrate layer, wherein the bottom substrate layer includes a bottom via electrically connected to the bottom anisotropic conductive layer below the die.

5. The package substrate of claim 4 further comprising a top via extending through the top substrate layer and the epoxy layer to a via end laterally offset from the bottom anisotropic conductive layer, wherein the bottom anisotropic conductive layer conducts electrical current along a horizontal axis between the top via and the bottom via.

6. The package substrate of claim 2 further comprising a conductive pad between the via and the anisotropic conductive layer, wherein the conductive pad includes a lateral pad dimension greater than a lateral via dimension of the via.

7. The package substrate of claim 2 , wherein the anisotropic conductive layer includes a conductive column extending along the vertical axis, wherein an insulating trench surrounds the conductive column, and wherein the via is electrically connected to the die pad through the conductive column.

8. A semiconductor package, comprising:

a package substrate including

a die including a die pad,

a top substrate layer including a via, and

an anisotropic conductive layer between the via and the die pad, wherein the via is electrically connected to the die pad through the anisotropic conductive layer, and

a memory die mounted on the top substrate layer of the package substrate, wherein the memory die includes an electrical bump connected to the via.

9. The semiconductor package of claim 8 , wherein the anisotropic conductive layer includes an anisotropic conductive adhesive, and wherein the anisotropic conductive adhesive conducts electrical current unidirectionally along a vertical axis between the via and the die pad.

10. The semiconductor package of claim 9 further comprising:

a bottom substrate layer under the die; and

an epoxy layer surrounding the die between the top substrate layer and the bottom substrate layer.

11. The semiconductor package of claim 10 further comprising a bottom anisotropic conductive layer between the die and the bottom substrate layer, wherein the bottom substrate layer includes a bottom via electrically connected to the bottom anisotropic conductive layer below the die.

12. The semiconductor package of claim 11 further comprising a top via extending through the top substrate layer and the epoxy layer to a via end laterally offset from the bottom anisotropic conductive layer, wherein the bottom anisotropic conductive layer conducts electrical current along a horizontal axis between the top via and the bottom via.

13. The semiconductor package of claim 9 further comprising a conductive pad between the via and the anisotropic conductive layer, wherein the conductive pad includes a pad dimension greater than a via dimension of the via.

14. The semiconductor package of claim 9 , wherein the anisotropic conductive layer includes a conductive column extending along the vertical axis, wherein an insulating trench surrounds the conductive column, and wherein the via is electrically connected to the die pad through the conductive column.

15. A package substrate, comprising:

a bottom substrate layer;

a die mounted on the bottom substrate layer, wherein the die includes a die pad;

a top substrate layer over the die, wherein the top substrate layer includes a via;

an anisotropic conductive layer between the die pad and the via, wherein the via is electrically connected to the die pad through the anisotropic conductive layer, wherein the anisotropic conductive layer includes an anisotropic conductive adhesive, and wherein the anisotropic conductive adhesive conducts electrical current unidirectionally along a vertical axis between the via and the die pad;

an epoxy layer surrounding the die between the top substrate layer and the bottom substrate layer; and

a bottom anisotropic conductive layer between the die and the bottom substrate layer, wherein the bottom substrate layer includes a bottom via electrically connected to the bottom anisotropic conductive layer below the die.

16. A package substrate, comprising:

a bottom substrate layer;

a die mounted on the bottom substrate layer, wherein the die includes a die pad;

a top substrate layer over the die, wherein the top substrate layer includes a via; and

an anisotropic conductive layer between the die pad and the via, wherein the via is electrically connected to the die pad through the anisotropic conductive layer, wherein the anisotropic conductive layer includes an anisotropic conductive adhesive, wherein the anisotropic conductive adhesive conducts electrical current unidirectionally along a vertical axis between the via and the die pad, wherein the anisotropic conductive layer includes a conductive column extending along the vertical axis, wherein an insulating trench surrounds the conductive column, and wherein the via is electrically connected to the die pad through the conductive column.

17. A method, comprising:

mounting a die on a bottom substrate layer, wherein the die includes a die pad, the die pad embedded in the die;

forming an anisotropic conductive layer over the die pad, the anisotropic conductive layer in direct physical contact with the die pad; and

forming a top substrate layer over the anisotropic conductive layer, wherein the top substrate layer includes a via electrically connected to the die pad through the anisotropic conductive layer.

18. The method of claim 17 , wherein the anisotropic conductive layer includes an anisotropic conductive adhesive, and wherein the anisotropic conductive adhesive conducts electrical current unidirectionally along a vertical axis between the via and the die pad.

19. The method of claim 18 further comprising forming an epoxy layer around the die, wherein the epoxy layer is between the top substrate layer and the bottom substrate layer.

20. The method of claim 19 further comprising forming a bottom anisotropic conductive layer between the die and the bottom substrate layer, wherein the bottom substrate layer includes a bottom via electrically connected to the bottom anisotropic conductive layer below the die.

21. The method of claim 20 further forming a top via through the top substrate layer and the epoxy layer, wherein the top via includes a via end laterally offset from the bottom anisotropic conductive layer, and wherein the bottom anisotropic conductive layer conducts electrical current along a horizontal axis between the top via and the bottom via.

22. The method of claim 18 further comprising forming a conductive column in the anisotropic conductive layer along the vertical axis, wherein the via is electrically connected to the die pad through the conductive column.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072792/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2023
From: DOMINGUEZ, JUAN EDUARDO; KIM, HYOUNG IL
To: INTEL CORPORATION
Reel/Frame 063714/0175 →
Continuity (2)
Continuation 16323402
Related Publication 20200388587A1 · Dec 10, 2020