Hybrid bonded interconnect bridging
A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.
1. A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising:
a first chiplet;
a second chiplet; and
an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond between metal interconnects of the interconnecting die and each of the first chiplet and the second chiplet, wherein the hybrid bond comprises a metal to dielectric pairing.
2. The chip of claim 1 , wherein the hybrid bond comprises an oxide bond and a copper bond.
3. The chip of claim 1 , wherein the interconnecting die comprises one or more trans-silicon via (TSV) connections between the first chiplet and the second chiplet.
4. The chip of claim 1 , wherein the interconnecting die comprises one or more physical intellectual property blocks facilitating communication external to the interconnecting die.
5. The chip of claim 1 , wherein the chip further comprises an epoxy molding layer, one or more conductive pillars coupled to the first chiplet or the second chiplet, and one or more conductive bumps applied to the one or more conductive pillars.
6. The chip of claim 1 , wherein the chip further comprises a dielectric layer and one or more through-dielectric vias coupled to the first chiplet or the second chiplet.
7. The chip of claim 6 , wherein the dielectric layer comprises fluorosilicate glass (FSG).
8. The chip of claim 1 , further comprising another interconnecting die bonded to one or more other chiplets using another hybrid bond.
9. An apparatus for hybrid bonded interconnect bridging for chiplet integration, the apparatus comprising:
one or more components, wherein at least one component is operatively coupled to a chip and the chip comprises:
a first chiplet;
a second chiplet; and
an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond between metal interconnects of the interconnecting die and each of the first chiplet and the second chiplet, wherein the hybrid bond comprises a metal to dielectric pairing.
10. The apparatus of claim 9 , wherein the hybrid bond comprises an oxide bond and a copper bond.
11. The apparatus of claim 9 , wherein the interconnecting die comprises one or more trans-silicon via (TSV) connections between the first chiplet and the second chiplet.
12. The apparatus of claim 9 , wherein the interconnecting die comprises one or more physical intellectual property blocks facilitating communication external to the interconnecting die.
13. The apparatus of claim 9 , wherein the chip further comprises an epoxy molding layer, one or more conductive pillars coupled to the first chiplet or the second chiplet, and one or more conductive bumps applied to the one or more conductive pillars.
14. The apparatus of claim 9 , wherein the chip further comprises a dielectric layer and one or more through-dielectric vias coupled to the first chiplet or the second chiplet.
15. The apparatus of claim 14 , wherein the dielectric layer comprises fluorosilicate glass (FSG).
16. The apparatus of claim 9 , wherein the chip further comprises another interconnecting die bonded to one or more other chiplets using another hybrid bond.
17. A method of hybrid bonded interconnect bridging for chiplet integration, the method comprising:
bonding an interconnecting die to a first chiplet and a second chiplet using a hybrid bond between metal interconnects of the interconnecting die and each of the first chiplet and the second chiplet, wherein the hybrid bond comprises a metal to dielectric pairing.
18. The method of claim 17 , wherein the hybrid bond comprises an oxide bond and a copper bond.
19. The method of claim 17 , wherein the interconnecting die comprises one or more trans-silicon via (TSV) connections between the first chiplet and the second chiplet.
20. The method of claim 17 , wherein the interconnecting die comprises one or more physical intellectual property blocks facilitating communication external to the interconnecting die.
21. The method of claim 17 , further comprising:
coupling one or more conductive pillars to the first chiplet and the second chiplet;
applying an epoxy molding layer to the first chiplet and the second chiplet; and
applying one or more conductive bumps to the one or more conductive pillars.
22. The method of claim 17 , further comprising applying, to the first chiplet and the second chiplet, a dielectric layer comprising one or more through-dielectric vias coupled to the first chiplet or the second chiplet.
23. The method of claim 22 , wherein the dielectric layer comprises fluorosilicate glass (FSG).
24. The method of claim 17 , further comprising bonding another interconnecting die to one or more other chiplets using another hybrid bond.