IP Library › Granted Patent US 11,296,026
Granted Patent B2
US 11,296,026 · App. 17/004,354 · Granted Apr 5, 2022

Semiconductor device and manufacturing method thereof

Inventors: Ming-Han Lee (Taipei, TW); Shau-Lin Shue (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L23/5283H01L21/76804H01L21/76816H01L21/76834H01L21/76843H01L21/76844H01L21/76847H01L21/76849H01L21/76877H01L21/76883H01L21/823475H01L23/5226H01L23/5329H01L23/53223H01L23/53238H01L23/53252H01L23/53266H01L23/53295
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,296,026
App. No.
17/004,354
Granted
Apr 5, 2022
Kind
B2
Abstract

A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.

Claims (46)

1. A semiconductor device, comprising:

a first metal wiring pattern disposed over a substrate;

a single layer of a first two-dimensional material layer covering sides and bottom of the first metal wiring pattern as seen in cross section;

a second metal wiring pattern disposed over the first metal wiring pattern and connected to the first metal wiring pattern;

a single layer of a second two-dimensional material layer covering sides and bottom of the second metal wiring pattern as seen in cross section,

wherein the second two-dimensional material layer is disposed between the second wiring pattern and the first wiring pattern; and

a single layer of a third two-dimensional material layer covering a top of the second metal wiring pattern,

wherein the second two-dimensional material layer and the third two-dimensional material layer are different materials.

2. The semiconductor device of claim 1 , wherein the first two-dimensional material layer includes graphene.

3. The semiconductor device of claim 1 , wherein the first two-dimensional material layer and the second two-dimensional material layer include a same material.

4. The semiconductor device of claim 1 , wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials.

5. The semiconductor device of claim 1 , wherein the first two-dimensional material layer and the second two-dimensional material layer include a transition metal dichalcogenide (TMD) or BN.

6. The semiconductor device of claim 5 , wherein the TMD includes one of MoS 2 , WS 2 and NbSe 2 .

7. A semiconductor device, comprising:

a first etch stop layer disposed over a substrate;

a first metal wiring pattern disposed over the first etch stop layer;

a single layer of a first two-dimensional material layer covering sides of the first metal wiring pattern and disposed between the first metal wiring pattern and the first etch stop layer as seen in cross section;

a single layer of a second two-dimensional material layer covering a first portion of a top of the first wiring pattern;

a single layer of a third two-dimensional material layer covering a second portion of the top of the first wiring pattern;

a second wiring pattern disposed over the first wiring pattern,

wherein the single layer of third two-dimensional material layer is disposed between the first wiring pattern and the second wiring pattern, and the single layer of the third two-dimensional material layer is disposed on sides of the second wiring pattern as seen in cross section, and

wherein the third two-dimensional material layer and the second two-dimensional material layer are different materials; and

a second etch stop layer disposed over second two-dimensional material layer.

8. The semiconductor device of claim 7 , further comprising a fourth two-dimensional material layer covering the top of the second metal wiring pattern.

9. The semiconductor device of claim 8 , wherein the third two-dimensional material layer and the fourth two-dimensional material layer include a same material.

10. The semiconductor device of claim 8 , wherein the third two-dimensional material layer and the fourth two-dimensional material layer are different materials.

11. The semiconductor device of claim 7 , wherein the second two-dimensional material layer covering the top of the first metal wiring pattern only covers the first metal wiring pattern.

12. The semiconductor device of claim 7 , wherein:

the first and second metal wiring patterns include Cu, and

the first two-dimensional material layer is in direct contact with a Cu surface of the first metal wiring pattern.

13. The semiconductor device of claim 7 , wherein the lower portion of the second metal wiring pattern is in direct contact with the third two-dimensional material layer.

14. The semiconductor device of claim 7 , wherein the first two-dimensional material layer and the third two-dimensional material layer include a same material.

15. The semiconductor device of claim 7 , wherein the first two-dimensional material layer and the third two-dimensional material layer are different materials.

16. A semiconductor device, comprising:

a first metal layer disposed over a substrate;

a single layer of a first two-dimensional material layer surrounding sides and bottom of the first metal layer as seen in cross section;

a single layer of a second two-dimensional material layer disposed over a top of the first metal layer as seen in the cross section,

wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials;

an etch stop layer disposed over the second two-dimensional material layer;

a second metal layer disposed over the first metal wiring pattern and connected to the first metal wiring pattern;

a single layer of a third two-dimensional material layer surrounding sides and a bottom of the second metal layer as seen in the cross section,

wherein the third two-dimensional material layer passes through the etch stop layer and the second two-dimensional material layer.

17. The semiconductor device of claim 16 , further comprising a fourth two-dimensional material layer covering the top of the second metal wiring pattern.

18. The semiconductor device of claim 17 , wherein the second two-dimensional material layer and the fourth two-dimensional layer include a same material.

19. The semiconductor device of claim 16 , wherein the first two-dimensional material layer and the third two-dimensional material layer include a same material.

20. The method according to claim 16 , wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: LEE, MING-HAN; SHUE, SHAU-LIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053614/0147 →
Continuity (3)
Continuation 16048921 · Jul 30, 2018
Division 15220078 · Jul 26, 2016
Related Publication 20200395299A1 · Dec 17, 2020