Pixel device on deep trench isolation (DTI) structure for image sensor

1. A CMOS image sensor, comprising:

a substrate having a front-side and a back-side opposite to the front-side;

a pixel region disposed within the substrate and comprising a P-N junction photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal;

a first trench isolation structure disposed at a peripheral of the pixel region, extending from the back-side of the substrate to a position within the substrate; and

a pixel device disposed at the front-side of the substrate directly overlying the first trench isolation structure, the pixel device comprising a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the first trench isolation structure;

a second trench isolation structure disposed from the front-side at an inner peripheral of the first trench isolation structure;

wherein the first trench isolation structure has a top surface locating at a position of the substrate vertically exceeding a bottom surface of the second trench isolation structure.

2. The CMOS image sensor of claim 1 , further comprising:

a third trench isolation structure disposed from the front-side at an outer peripheral of the first trench isolation structure;

wherein the pixel device is disposed between the second trench isolation structure and the third trench isolation structure.

3. The CMOS image sensor of claim 2 , wherein the S/D regions of the pixel device have bottom surfaces locating at a position of the substrate higher than bottom surfaces of the second trench isolation structure and the third trench isolation structure.

4. The CMOS image sensor of claim 2 , wherein the S/D regions of the pixel device have bottom surfaces laterally aligned with bottom surfaces of the second trench isolation structure and the third trench isolation structure.

5. The CMOS image sensor of claim 2 , wherein the first trench isolation structure has an outermost sidewall contacting a bottom surface of the second trench isolation structure and an innermost sidewall contacting a bottom surface of the third trench isolation structure.

6. The CMOS image sensor of claim 2 , wherein the pixel device is a source follower transistor, a reset transistor, or a row select transistor.

7. The CMOS image sensor of claim 2 , wherein the pixel device has outermost sidewalls of the S/D regions contacting an outermost sidewall of the second trench isolation structure and innermost sidewalls of the S/D regions contacting innermost sidewall of the third trench isolation structure.

8. The CMOS image sensor of claim 1 , wherein the first trench isolation structure comprises silicon oxide.

9. The CMOS image sensor of claim 1 , further comprising:

an anti-reflection layer disposed on the back-side of the substrate;

wherein the anti-reflection layer has a non-flat bottom surface.

10. The CMOS image sensor of claim 9 , further comprising:

a conductive column disposed at a center region of the first trench isolation structure and electrically connecting the source/drain (S/D) regions of the pixel device to a contact at the back-side of the substrate through the anti-reflection layer.

11. The CMOS image sensor of claim 1 , wherein the source/drain (S/D) regions of the pixel device comprise a silicide layer locating at an upper region of the source/drain (S/D) regions.

12. The CMOS image sensor of claim 1 , further comprising:

a floating diffusion well disposed within the substrate between the P-N junction photodiode and the first trench isolation structure; and

a transfer gate electrode arranged on the front-side of the substrate at a position laterally between the P-N junction photodiode and the floating diffusion well and separated from the substrate by a gate dielectric.

13. The CMOS image sensor of claim 12 , wherein the transfer gate electrode and the gate dielectric extend to a position within the substrate.

14. A CMOS image sensor, comprising:

a substrate having a front-side and a back-side opposite to the front-side;

a pixel region disposed within the substrate and comprising a P-N junction photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal;

a first shallow trench isolation (STI) structure and a second STI structure extending from the front-side of the substrate surrounding the P-N junction photodiode;

a deep trench isolation (DTI) structure disposed between the first STI structure and the second STI structure and extending from the back-side of the substrate to meet the first STI structure and the second STI structure within the substrate; and

a pixel device disposed at the front-side of the substrate between the first and second STI structures, the pixel device comprising a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate;

wherein the pixel device directly contacts a top surface of the DTI structure.

15. The CMOS image sensor of claim 14 , wherein the pixel device directly contacts a top surface of the DTI structure.

16. The CMOS image sensor of claim 14 , wherein S/D regions of the pixel device directly contact sidewalls of the first and second STI structures.

17. The CMOS image sensor of claim 14 , wherein a bisecting line of the first STI structure and the second STI structure laterally bisects the DTI structure.

18. The CMOS image sensor of claim 14 , wherein the pixel device is a source follower transistor, a reset transistor, or a row select transistor.

19. A CMOS image sensor, comprising:

a first shallow trench isolation (STI) structure and a second STI structure disposed at a peripheral of a pixel region from a front-side of a substrate;

a P-N junction photodiode disposed in the pixel region from the front-side of the substrate;

a transfer gate structure disposed aside of the P-N junction photodiode and a floating diffusion well disposed at one side of the transfer gate structure opposite to the P-N junction photodiode;

a gate structure for a pixel device disposed between the first STI structure and the second STI structure and S/D regions alongside the gate structure of the pixel device; and

a deep trench isolation structure disposed from a back-side of the substrate extending into the substrate and between the first STI structure and the second STI structure;

wherein the deep trench isolation structure directly contacts the S/D regions of the pixel device.

20. The CMOS image sensor of claim 19 , wherein the deep trench isolation structure directly contacts the S/D regions of the pixel device.