Architecture design and process for 3D logic and 3D memory
Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.
1. A method of forming a circuit, the method comprising:
on a first substrate that has a front side opposite a backside, forming a first dielectric layer on the front side, forming low-voltage devices on the first dielectric layer, and forming a first wiring plane above the low-voltage devices;
on a second substrate that has a front side opposite a backside, forming high-voltage devices on the front side, forming memory devices above the high-voltage devices, and forming a second wiring plane above the memory devices; and
aligning the first wiring plane to be in contact with the second wiring plane and joining the first substrate with the second substrate to form a combined substrate.
2. The method of claim 1 , wherein
on the second substrate that has a front side opposite a backside, before forming the high-voltage devices on the first side, forming a second dielectric layer on the front side, forming the high-voltage devices on the second dielectric layer, then forming the memory devices above the high-voltage devices, and forming the second wiring plane above the memory devices.
3. The method of claim 1 , further comprising removing bulk substrate material from the backside of the first substrate until uncovering the first dielectric layer.
4. The method of claim 3 , further comprising forming a third wiring plane using the first dielectric layer.
5. The method of claim 1 , wherein forming includes using different annealing temperatures on the first substrate compared to the second substrate.
6. The method of claim 1 , wherein the low-voltage devices include three-dimensional (3D) devices, stacked devices, or lateral gate-all-around devices.
7. The method of claim 1 , wherein the forming of first and second wiring planes includes depositing oxide, using a photo mask to etch trenches and vias or adding contacts.
8. The method of claim 1 , wherein the high-voltage devices include planar or FinFET devices.
9. A method of forming an integrated circuit, the method comprising:
on a first substrate that has a front side opposite a backside, forming low-voltage devices on the front side, and forming a first wiring plane above the low-voltage devices;
on a second substrate that has a front side opposite a backside, forming high-voltage devices on the front side, forming first memory devices above the high-voltage devices, and forming a second wiring plane above the first memory devices; and
aligning the first wiring plane to be in contact with the second wiring plane and joining the first substrate with the second substrate to form a combined substrate.
10. The method of claim 9 , further comprising:
reducing a thickness of bulk substrate material from the first substrate;
converting remaining bulk substrate material of the first substrate to a first dielectric layer; and
forming a third wiring plane using the first dielectric layer.
11. The method of claim 9 , further comprising:
reducing a thickness of bulk substrate material from the first substrate;
forming second memory devices using remaining bulk substrate material of the first substrate; and
forming a fourth wiring plane above the second memory devices.
12. The method of claim 9 , wherein forming includes using different annealing temperatures on the first substrate compared to the second substrate.
13. The method of claim 9 , wherein the low-voltage devices include three-dimensional (3D) devices, stacked devices, or lateral gate-all-around devices.
14. The method of claim 9 , wherein the forming of first and second wiring planes includes depositing oxide, using a photo mask to etch trenches and vias or adding contacts.
15. A method of forming a circuit, the method comprising:
on a first substrate that has a front side opposite a backside, forming a first dielectric layer on the front side, forming low-voltage devices on the first dielectric layer, and forming a first wiring plane above the first low-voltage devices;
on a second substrate that has a front side opposite a backside, forming a second dielectric layer on the front side, forming high-voltage devices on the second dielectric layer, and forming a second wiring plane above the high-voltage devices; and
on a third substrate that has a front side opposite a backside, forming a third dielectric layer on the front side, forming memory devices on the third dielectric layer, and forming a third wiring plane above the memory devices;
aligning the third wiring plane to be in contact with the second wiring plane and joining the third substrate with the second substrate to form a combined substrate;
removing bulk substrate material from the backside of the second substrate until uncovering the second dielectric layer;
forming a fourth wiring plane using the first dielectric layer; and
aligning the second wiring plane to be in contact with the fourth wiring plane and joining the first substrate with the combined substrate.
16. The method of claim 15 , wherein forming includes using different annealing temperatures on the first substrate, second substrate and third substrate.
17. The method of claim 15 , wherein the low-voltage devices include three-dimensional (3D) devices, stacked devices, or lateral gate-all-around devices.
18. The method of claim 15 , wherein the forming of first, second and third wiring planes includes depositing oxide, using a photo mask to etch trenches and vias or adding contacts.
19. The method of claim 15 , wherein the order of stacking the first, second and third substrates is different.
20. The method of claim 15 , wherein the forming a fourth wiring plane comprises:
reducing a thickness of bulk substrate material from the first substrate;
converting remaining bulk substrate material of the first substrate to the first dielectric layer; and
forming the fourth wiring plane using the first dielectric layer.