IP Library Granted Patent US 11,502,100
Granted Patent B2
US 11,502,100 · App. 17/011,451 · Granted Nov 15, 2022

Semiconductor device and method of manufacturing the same

Inventors: Kaito Shirai (Yokkaichi, JP); Hideto Takekida (Nagoya, JP); Tatsuo Izumi (Yokkaichi, JP); Reiko Shamoto (Nagoya, JP); Takahisa Kanemura (Yokohama, JP); Shigeo Kondo (Yokkaichi, JP)
Assignee: Kioxia Corporation
H01L27/11582H01L27/1157H01L27/11565H01L29/40117H01L29/517
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Quick Facts
Patent No.
US 11,502,100
App. No.
17/011,451
Granted
Nov 15, 2022
Kind
B2
Abstract

According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

Claims (35)

1. A semiconductor device comprising:

a stacked body including:

a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator,

a second stacked portion including a plurality of second electrode layers stacked in the first direction via a second insulator and being disposed separately from the first stacked portion in the first direction, and

a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion, and having a dielectric constant higher than a dielectric constant of the first and second insulators;

a first semiconductor body extending in the first stacked portion in the first direction;

a first charge storage portion provided between the first semiconductor body and one of the plurality of first electrode layers;

a second semiconductor body extending in the second stacked portion in the first direction;

a second charge storage portion provided between the second semiconductor body and one of the plurality of second electrode layers; and

a third semiconductor body extending in the connection portion and being in contact with the first semiconductor body and the second semiconductor body,

the first, second, and third semiconductor bodies respectively having a circular outer peripheral shape in a plane perpendicular to the first direction,

a maximum width, in a second direction perpendicular to the first direction, of the third semiconductor body being larger than a width, in the second direction, of a lower end of the second semiconductor body.

2. The device according to claim 1 , wherein the third semiconductor body includes a corner portion surrounded by the connection portion.

3. The device according to claim 1 , wherein the high dielectric layer is provided in the entire connection portion.

4. A semiconductor device comprising:

a stacked body including:

a first electrode layer,

a first insulator provided on the first electrode layer,

a connection portion provided on the first insulator, the connection portion including a high dielectric layer having a dielectric constant higher than a dielectric constant of the first insulator, and

a second electrode layer provided above the connection portion;

first and second semiconductor bodies provided adjacent to each other in the stacked body, and extending in a first direction through the first electrode layer, the first insulator, the connection portion, and the second electrode layer;

a first charge storage portion provided between the first semiconductor body and the first electrode layer;

a second charge storage portion provided between the first semiconductor body and the second electrode layer;

a third charge storage portion provided between the second semiconductor body and the first electrode layer; and

a fourth charge storage portion provided between the second semiconductor body and the second electrode layer,

a shortest distance between the first and second semiconductor bodies in a portion surrounded by the connection portion being shorter than a shortest distance between the first and second semiconductor bodies in a portion surrounded by the first insulator.

5. The device according to claim 4 , wherein the high dielectric layer is provided in the entire connection portion.

6. The device according to claim 4 , wherein

the connection portion includes:

the high dielectric layer,

a first insulating layer between the first electrode layer and the high dielectric layer, and

a second insulating layer between the high dielectric layer and the second electrode layer.

7. The device according to claim 6 , wherein a thickness of the high dielectric layer is thinner than a thickness of the first insulating layer and a thickness of the second insulating layer.

8. The device according to claim 4 , wherein the high dielectric layer includes a hafnium oxide.

9. The device according to claim 4 , wherein the first semiconductor body includes a corner portion surrounded by the connection portion, and the second semiconductor body includes a corner portion surrounded by the connection portion.

Assignments (1)
CHANGE OF NAME Recorded Jan 7, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058664/0544 →
Continuity (3)
Continuation 16351832 · Mar 13, 2019
Continuation PCTJP2016077817 · Sep 21, 2016
Related Publication 20200403000A1 · Dec 24, 2020