IP Library Granted Patent US 11,417,679
Granted Patent B2
US 11,417,679 · App. 17/011,517 · Granted Aug 16, 2022

Three-dimensional semiconductor memory device

Inventor: Shinya Arai (Yokkaichi, JP)
Assignee: Kioxia Corporation
H01L27/11582H01L23/528H01L23/53257H01L23/53271H01L27/11565H01L27/11578H01L29/0649H01L29/0847H01L29/45H01L29/792
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Quick Facts
Patent No.
US 11,417,679
App. No.
17/011,517
Granted
Aug 16, 2022
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Claims (54)

1. A semiconductor memory device comprising:

a substrate;

an insulating layer provided above the substrate;

a conductive layer including a first film and a second film, the second film being provided above the insulating layer and the first film being provided on the second film;

a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked from each other in a first direction;

a semiconductor body extending in the first direction through the stacked body and including a lower end portion below the stacked body;

a memory portion provided between the semiconductor body and one of the plurality of electrode layers; and

a bit line electrically connected to an upper end portion of the semiconductor body above the stacked body,

the lower end portion of the semiconductor body projecting into the first film of the conductive layer and being in direct contact with the first film, the lower end portion of the semiconductor body being provided above an upper surface of the second film of the conductive layer, the first film including silicon, and the second film including metal,

wherein one of the plurality of electrode layers closest to the conductive layer in the first direction is a source side selection gate.

2. The device according to claim 1 , wherein the first film includes polysilicon and the second film includes tungsten.

3. The device according to claim 1 , wherein:

the semiconductor body has a cylindrical shape extending in the first direction and a core insulator is provided inside the semiconductor body of cylindrical shape.

4. The device according to claim 1 , further comprising:

a source layer coupled to the semiconductor body via the conductive layer, the lower end portion of the semiconductor body being electrically connectable to the source layer via the conductive layer without intervening of any other semiconductor body.

5. The device according to claim 1 , further comprising:

a plurality of insulating films extending in the first direction through the stacked body to reach the conductive laver.

6. The device according to claim 5 , wherein the insulating films further extend in a second direction crossing the first direction and a bit line extending direction, the insulating films dividing the stacked body in the bit line extending direction.

7. A semiconductor memory device comprising:

a substrate;

an insulating layer provided above the substrate;

a conductive layer including a first film and a second film, the second film being provided above the insulating layer and the first film being provided on the second film;

a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked from each other in a first direction;

a semiconductor body extending in the first direction through the stacked body and including a lower end portion below the stacked body;

a memory portion provided between the semiconductor body and one of the plurality of electrode layers; and

a bit line electrically connected to an upper end portion of the semiconductor body above the stacked body,

both of the semiconductor body and the first film including silicon, and the second film including metal, and

the first film being formed as a different body from the semiconductor body and being in direct contact with the lower end portion of the semiconductor body, an interface being formed between the lower end portion of the semiconductor body and the first film of the conductive layer,

wherein one of the plurality of electrode layers closest to the conductive layer in the first direction is a source side selection gate.

8. The device according to claim 7 , wherein the first film includes polysilicon and the second film includes tungsten.

9. The device according to claim 7 , wherein:

the semiconductor body has a cylindrical shape extending in the first direction and a core insulator is provided inside the semiconductor body of cylindrical shape.

10. The device according to claim 7 , further comprising:

a source layer coupled to the semiconductor body via the conductive layer, the lower end portion of the semiconductor body being electrically connectable to the source layer via the conductive layer without intervening of any other semiconductor body.

11. The device according to claim 7 , further comprising:

a plurality of insulating films extending in the first direction through the stacked body to reach the conductive layer.

12. The device according to claim 11 , wherein the insulating films further extend in a second direction crossing the first direction and a bit line extending direction, the insulating films dividing the stacked body in the bit line extending direction.

13. A semiconductor memory device comprising:

a substrate;

an insulating layer provided above the substrate;

a conductive layer including a first film and a second film, the second film being provided above the insulating layer and the first film being provided on the second film;

a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked from each other in a first direction;

a semiconductor body having a cylindrical shape extending in the first direction through the stacked body and including a lower end portion below the stacked body;

a core insulator provided inside the semiconductor body;

a memory portion provided between the semiconductor body and one of the plurality of electrode layers; and

a bit line electrically connected to an upper end portion of the semiconductor body above the stacked body,

the lower end portion of the semiconductor body being provided above an upper surface of the second film of the conductive layer, the lower end portion of the semiconductor body being in direct contact with the first film, the lower end portion of the semiconductor body contacting with the first film being interposed between the first film of the conductive layer and the core insulator in the first direction, the first film including silicon, and the second film including metal,

wherein one of the plurality of electrode layers closest to the conductive layer in the first direction is a source side selection gate.

14. The device according to claim 13 , wherein the first film includes polysilicon and the second film includes tungsten.

15. The device according to claim 13 , further comprising:

a source layer coupled to the semiconductor body via the conductive layer, the lower end portion of the semiconductor body being electrically connectable to the source layer via the conductive layer without intervening of any other semiconductor body.

16. The device according to claim 13 , further comprising:

a plurality of insulating films extending in the first direction through the stacked body to reach the conductive layer.

17. The device according to claim 16 , wherein the insulating films further extend in a second direction crossing the first direction and a bit line extending direction, the insulating films dividing the stacked body in the bit line extending direction.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Sep 7, 2021
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 057425/0547 →
CHANGE OF NAME Recorded Sep 7, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057425/0748 →
Continuity (5)
Continuation 16137702 · Sep 21, 2018
Continuation 15344021 · Nov 4, 2016
Continuation 14597580 · Jan 15, 2015
Provisional Application 62047369 · Sep 8, 2014
Related Publication 20200403001A1 · Dec 24, 2020