IP Library Granted Patent US 11,862,648
Granted Patent B2
US 11,862,648 · App. 17/012,683 · Granted Jan 2, 2024

Optoelectronic device arranged as a multi-spectral light sensor having a photodiode array with aligned light blocking layers and n-well regions

Inventors: Koon-Wing Tsang (Fremont, CA); Yuh-Min Lin (San Ramon, CA)
Assignee: VISHAY INTERTECHNOLOGY, INC.
H01L27/1446G01J3/0229G01J3/2803H01L31/02164H01L31/02165H01L31/1013G01J2003/2806
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Quick Facts
Patent No.
US 11,862,648
App. No.
17/012,683
Granted
Jan 2, 2024
Kind
B2
Abstract

An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Claims (17)

1. A method for manufacturing an optoelectronic device, comprising:

forming a first layer of light-transmissive material over a photodiode array, the photodiode array including a plurality of photodiodes, each photodiode having a respective n-well region;

forming a plurality of first trenches in the first layer of light-transmissive material;

forming a layer of light-blocking material in the plurality of first trenches;

forming a first metal layer over the first layer of light-transmissive material and the layer of light-blocking material;

forming a second layer of light-transmissive material over the first metal layer;

forming a plurality of second trenches in the second layer of light-transmissive material, each of the second trenches having a different depth;

forming a respective second metal layer in each of the plurality of second trenches; and

filling each of the second trenches with a light-transmissive material after the respective second trench's respective second metal layer is formed in the second trench.

2. The method of claim 1 , further comprising forming processing circuitry for processing one or more signals that are generated by the photodiode array, wherein the processing circuitry is formed on a same die as the photodiode array and the layer of light-blocking material is formed simultaneously with back end of line (BEOL) metallization that is performed on the processing circuitry.

3. The method of claim 2 , wherein the processing circuitry includes at least one of complementary metal-oxide-semiconductor (CMOS) circuitry and bipolar complementary metal-oxide-semiconductor (BiCMOS) circuitry.

4. The method of claim 2 , wherein the processing circuitry includes at least one of a switch, an analog-to-digital converter, an amplifier, a processor, and an input-output interface.

5. The method of claim 1 , wherein the plurality of first trenches define a plurality of guide members.

6. The method of claim 5 , wherein each photodiode of the plurality of photodiodes has a respective n+ region, and wherein each guide member of the plurality of guide members is aligned with the n+ region of a respective photodiode of the plurality of photodiodes.

7. The method of claim 6 , wherein each guide member is disposed over a different respective n+ region.

8. The method of claim 5 , wherein the layer of light-blocking material is formed so as to separate adjacent guide members of the plurality of guide members from each other.

9. The method of claim 1 , wherein the respective layer of light-blocking material is formed so as to be disposed over and substantially cover an entirety of an upper surface of the respective n-well region of the plurality of photodiodes.

Assignments (3)
SECURITY INTEREST Recorded Sep 16, 2025
From: VISHAY DALE ELECTRONICS, INC. (N/K/A VISHAY DALE ELECTRONICS, LLC); VISHAY-SILICONIX (N/K/A SILICONIX INCORPORATED); VISHAY GENERAL SEMICONDUCTOR INC. (N/K/A VISHAY GSI, INC.); VISHAY GENERAL SEMICONDUCTOR, LLC (N/K/A VISHAY GSI, INC.); VISHAY INTERTECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 072272/0193 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2020
From: TSANG, KOON-WING; LIN, YUH-MIN
To: VISHAY CAPELLA MICROSYSTEMS (TAIWAN) LIMITED
Reel/Frame 054550/0479 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2020
From: VISHAY CAPELLA MICROSYSTEMS (TAIWAN) LIMITED
To: VISHAY INTERTECHNOLOGY, INC.
Reel/Frame 054600/0862 →
Continuity (2)
Division 15941855 · Mar 30, 2018
Related Publication 20200403013A1 · Dec 24, 2020