IP Library Granted Patent US 11,562,945
Granted Patent B2
US 11,562,945 · App. 17/020,473 · Granted Jan 24, 2023

Semiconductor device having a spacer structure in a conductive layer and a contact structure in the spacer structure

Inventors: Linchun Wu (Wuhan, CN); Kun Zhang (Wuhan, CN); Zhong Zhang (Wuhan, CN); Wenxi Zhou (Wuhan, CN); Zhiliang Xia (Wuhan, CN)
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
H01L23/481H01L21/4814H01L27/1157H01L27/11565H01L27/11573H01L27/11582
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Quick Facts
Patent No.
US 11,562,945
App. No.
17/020,473
Granted
Jan 24, 2023
Kind
B2
Abstract

Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

Claims (51)

1. A semiconductor device, comprising:

an insulating layer;

a conductive layer over the insulating layer;

a spacer structure through the conductive layer and in contact with the insulating layer;

a first contact structure in the spacer structure and extending vertically through the insulating layer; and

a channel structure comprising a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer,

wherein the first contact structure comprises a first contact portion and a second contact portion in contact with each other, and

an upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

2. The semiconductor device of claim 1 , wherein the conductive layer comprises polysilicon.

3. The semiconductor device of claim 1 , wherein a lateral cross-sectional area of the second contact portion is greater than or equal to a lateral cross-sectional area of the first contact portion.

4. The semiconductor device of claim 1 , further comprises:

a memory stack comprising interleaved stack conductive layers and stack dielectric layers over the conductive layer and apart from the first contact structure, wherein the channel structure extends through the memory stack into the conductive layer;

and

a second contact structure extending vertically in the insulating layer and in contact with the conductive layer.

5. The semiconductor device of claim 4 , wherein

the channel structure further comprises a memory layer in contact with and surrounding the semiconductor channel; and

a lower portion of the memory layer is disconnected to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

6. The semiconductor device of claim 1 , wherein the spacer structure comprises a dielectric material.

7. The semiconductor device of claim 1 , wherein the first contact structure electrically connects a peripheral circuit and a contact pad on opposite sides of the insulating and conductive layers.

8. The semiconductor device of claim 4 , wherein the first contact structure is electrically connected to the second contact structure.

9. The semiconductor device of claim 1 , wherein the spacer structure electrically insulates the second contact portion from the conductive layer.

10. A semiconductor device, comprising:

an insulating layer;

a conductive layer over the insulating layer;

a spacer structure in the conductive layer and in contact with the insulating layer, the spacer structure covering an entirety side surface of the conductive layer;

a first contact structure in the spacer structure and extending vertically through the insulating layer; and

a channel structure comprising a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer,

wherein the first contact structure comprises a first contact portion and a second contact portion in contact with each other, and

an upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

11. The semiconductor device of claim 10 , wherein the conductive layer comprises polysilicon.

12. The semiconductor device of claim 10 , wherein a lateral cross-sectional area of the second contact portion is greater than or equal to a lateral cross-sectional area of the first contact portion.

13. The semiconductor device of claim 10 , further comprises:

a memory stack comprising interleaved stack conductive layers and stack dielectric layers over the conductive layer and apart from the first contact structure, wherein the channel structure extends through the memory stack into the conductive layer;

and

a second contact structure extending vertically in the insulating layer and in contact with the conductive layer.

14. The semiconductor device of claim 13 , wherein

the channel structure further comprises a memory layer in contact with and surrounding the semiconductor channel; and

a lower portion of the memory layer is disconnected to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

15. The semiconductor device of claim 10 , wherein the spacer structure comprises a dielectric material.

16. The semiconductor device of claim 10 , wherein the first contact structure electrically connects a peripheral circuit and a contact pad on opposite sides of the insulating and conductive layers.

17. The semiconductor device of claim 13 , wherein the first contact structure is electrically connected to the second contact structure.

18. The semiconductor device of claim 10 , wherein the spacer structure electrically insulates the second contact portion from the conductive layer.

19. A semiconductor device, comprising:

an insulating layer;

a conductive layer over the insulating layer;

a spacer structure in the conductive layer and in contact with the insulating layer, a lower surface of the spacer structure is coplanar with a lower surface of the conductive layer;

a first contact structure in the spacer structure and extending vertically through the insulating layer; and

a channel structure comprising a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer,

wherein the first contact structure comprises a first contact portion and a second contact portion in contact with each other, and

an upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

20. The semiconductor device of claim 19 , wherein the spacer structure electrically insulates the second contact portion from the conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: WU, LINCHUN; ZHANG, KUN; ZHANG, ZHONG; ZHOU, WENXI; XIA, ZHILIANG
To: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Reel/Frame 053765/0978 →
Continuity (2)
Continuation PCTCN2020106068 · Jul 31, 2020
Related Publication 20220037234A1 · Feb 3, 2022
Cited By (3)
US 12,471,284 US 12,519,038 US 12,598,754