Partial directional etch method and resulting structures

1. A method comprising:

forming a dummy gate and an adjacent structure, the dummy gate including a first portion having vertical sidewalls and a footing portion wherein the sidewalls widen outwards;

using a directional etch, removing some but not all of the dummy gate to form a trench, wherein the footing portion of the dummy gate remains and protects the adjacent structure; and

forming a gate electrode in the trench.

2. The method of claim 1 , further comprising using an isotropic etch to remove a top portion of the dummy gate before the step of using a direction etch.

3. The method of claim 1 , wherein the step of forming a dummy gate results in the dummy gate having a footing region that widens outwards from a nominal edge of the dummy gate.

4. The method of claim 3 , wherein the step of removing some but not all of the dummy gate includes leaving only the footing region of the dummy gate.

5. The method of claim 3 , wherein the step of removing some but not all of the dummy gate includes leaving a portion of the dummy gate that extends from a first sidewall of the trench to a second sidewall of the trench.

6. The method of claim 1 , wherein the dummy gate extends over a fin, and further comprising:

etching a portion of the fin adjacent the dummy gate to form a fin recess; and

epitaxially growing the adjacent structure in the fin recess.

7. The method of claim 2 , wherein the dummy gate extends over a fin, and further wherein:

the step of using an isotropic etch to remove a top portion of the dummy gate includes etching the dummy gate back to a level of the topmost surface of the fin; and

the step of using a directional etch, removing some but not all of the dummy gate includes etching the dummy gate back along sidewalls of the fin.

8. The method of claim 1 , wherein the directional etch is a plasma etch performed using ion bombardment.

9. The method of claim 8 , wherein the directional etch is performed using:

an etch gas selected from the group consisting of chlorine, fluorine, C x F y , and combinations thereof;

a passivation gas selected from the group consisting of oxygen-based gas and HBr, and combinations thereof; and

an inert carrier gas.

10. A method comprising:

forming a fin extending from a semiconductor substrate;

depositing over the fin a dummy gate material;

patterning the dummy gate material to form a dummy gate extending over a top of the fin and along sidewalls of the fin;

depositing a spacer material on the dummy gate and patterning the spacer material to form spacers on respective sidewalls of the dummy gate;

using the dummy gate and spacers as a mask, etching portions of the fin to form fin recesses;

filling respective fin recesses with source/drain regions;

depositing a dielectric layer to surround the dummy gate, the source/drain regions, and the fin;

isotropically etching the dummy gate to remove a top portion of the dummy gate and to leave a bottom portion of the dummy gate;

anisotropically etching the bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and to leave a remnant portion of the dummy gate; and

forming on the remnant portion of the dummy gate a metal gate electrode.

11. The method of claim 10 , wherein the step of isotropically etching the dummy gate includes performing a wet etch or remote plasma etch.

12. The method of claim 11 , wherein the step of anisotropically etching the bottom portion of the dummy gate includes performing a plasma etch with ion bombardment to remove some but not all of the bottom portion while leaving a remnant portion of the dummy gate.

13. The method of claim 12 , wherein the steps of isotropically etching the dummy gate and of anisotropically etching the bottom portion of the dummy gate forms a trench in the dielectric layer and further wherein the remnant portion of the dummy gate remains at bottom corners of the trench.

14. The method of claim 13 , wherein the remnant portion of the dummy gate extends from a first sidewall of the trench to a second sidewall of the trench.

15. The method of claim 10 , wherein the step of forming on the remnant portion of the dummy gate a metal gate electrode includes forming a gate dielectric directly on the remnant portion of the dummy gate.

16. The method of claim 10 , wherein the step of filling respective fin recesses with source/drain regions includes epitaxially growing semiconductor material in the respective fin recesses.

17. The method of claim 10 , wherein the step of isotropically etching the dummy gate to remove a top portion of the dummy gate includes timing the isotropic etch to remove dummy gate material to a level substantially co-planar with a top surface of the fin.

18. A device comprising:

a fin extending upwards from a substrate;

an isolation material formed over the fin;

a gate, including a gate dielectric, within a trench in the isolation material, the gate extending over a top and sidewalls of the fin; and

a polysilicon material extending along a bottom portion of the trench, the polysilicon material being interjacent the gate dielectric and the substrate in a direction perpendicular to the major surface of the substrate.

19. The device of claim 18 , wherein the substrate includes a dielectric layer top surface.

20. The device of claim 18 , wherein the polysilicon material is interjacent the gate and a source/drain region of the device.