IP Library Granted Patent US 11,695,049
Granted Patent B2
US 11,695,049 · App. 17/029,075 · Granted Jul 4, 2023

High electron mobility transistor and method for forming the same

Inventors: Chih-Tung Yeh (Taoyuan, TW); Chun-Liang Hou (Hsinchu County, TW); Wen-Jung Liao (Hsinchu, TW); Chun-Ming Chang (Kaohsiung, TW); Yi-Shan Hsu (Taipei, TW); Ruey-Chyr Lee (Taichung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/4175H01L29/66462H01L29/7786H01L29/0684H01L29/2003H01L29/205H01L29/401
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Quick Facts
Patent No.
US 11,695,049
App. No.
17/029,075
Granted
Jul 4, 2023
Kind
B2
Abstract

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

Claims (29)

1. A high electron mobility transistor, comprising:

a substrate;

a mesa structure disposed on the substrate, wherein the mesa structure comprises a channel layer and a barrier layer on the channel layer;

a passivation layer disposed on the mesa structure;

at least a contact structure disposed in the passivation layer and the mesa structure, wherein the contact structure comprises a body portion and a plurality of protruding portions, the body portion penetrates through the passivation layer and a portion of the barrier layer, the plurality of protruding portions penetrate through the barrier layer and a portion of the channel layer, wherein a bottom surface of the body portion is lower than an upper surface of the barrier layer and higher than a bottom surface of the barrier layer; and

a gate structure disposed on the mesa structure and between the contact structure and another one of the contact structure, wherein the gate structure comprises:

a semiconductor gate layer directly disposed on the barrier layer of the mesa structure and covered by the passivation layer; and

a gate metal layer through the passivation layer to directly contact a top surface of the semiconductor gate layer.

2. The high electron mobility transistor according to claim 1 , wherein the plurality of protruding portions are arranged along a first direction and a second direction to form an array in a top plane view, the first direction and the second direction are perpendicular.

3. The high electron mobility transistor according to claim 2 , wherein the plurality of protruding portions are aligned along the second direction and are staggered along the first direction.

4. The high electron mobility transistor according to claim 1 , wherein the plurality of protruding portions of the contact structure and the gate structure extend along a same direction in a top plane view.

5. The high electron mobility transistor according to claim 1 , wherein the plurality of protruding portions of the contact structure extend along a direction that is perpendicular to a direction along that the gate structure extends.

6. The high electron mobility transistor according to claim 1 , the body portion of the contact structure overlaps two edges of the mesa structure.

7. The high electron mobility transistor according to claim 1 , the body portion and the plurality of protruding portions of the contact structure are of a one-piece structure.

8. The high electron mobility transistor according to claim 1 , wherein a material of the contact structure is selected from a group consisting of gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), Palladium (Pd), platinum (Pt), a compounds of the above materials, a composite layer of the above materials, and an alloy of the above materials.

9. The high electron mobility transistor according to claim 1 , wherein a material of the channel layer is selected from a group consisting of gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), and a combination thereof.

10. The high electron mobility transistor according to claim 1 , wherein a material of the barrier layer is selected from a group consisting of aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlInGaN), aluminum nitride (AlN), and a combination thereof.

11. The high electron mobility transistor according to claim 1 , wherein a material of the passivation layer is selected from a group consisting of aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), boron nitride (BN), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), zirconia (ZrO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), lutetium oxide (Lu 2 O 3 ), lanthanum oxide (LaLuO 3 ), and a combination thereof.

12. A method for forming a high electron mobility transistor, comprising:

providing a substrate;

forming a mesa structure on the substrate, wherein the mesa structure has a channel layer and a barrier layer disposed on the channel layer;

forming a semiconductor gate layer on the barrier layer of the mesa structure;

forming a passivation layer covering the substrate and the mesa structure and the semiconductor gate layer;

forming at least a first opening at a side of the semiconductor gate layer, wherein the first opening penetrates through the passivation layer and extends into part of the barrier layer, wherein a bottom surface of the first opening is lower than an upper surface of the barrier layer and higher than a bottom surface of the barrier layer;

forming a plurality of second openings, wherein the plurality of second openings are connected to a bottom surface of the first opening and penetrate through the barrier layer and a portion of the channel layer;

forming a metal layer in the first opening and the plurality of second openings thereby forming a contact structure; and

forming a gate metal layer through the passivation layer to directly contact a top surface of the semiconductor gate layer.

13. The method for forming a high electron mobility transistor according to claim 12 , wherein the plurality of second openings are arranged along a first direction and a second direction to form an array in a top plane view, the first direction and the second direction are perpendicular.

14. The method for forming a high electron mobility transistor according to claim 12 , wherein the first opening overlaps two edges of the mesa structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2020
From: YEH, CHIH-TUNG; HOU, CHUN-LIANG; LIAO, WEN-JUNG; CHANG, CHUN-MING; HSU, YI-SHAN; LEE, RUEY-CHYR
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 053852/0159 →
Priority Claims (1)
CN 202010799660.6 · Aug 11, 2020 · national
Continuity (1)
Related Publication 20220052166A1 · Feb 17, 2022
Cited By (2)
US 12,206,000 US 12,266,701