Voltage generation circuit which is capable of executing high-speed boost operation
According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.
1. A non-volatile semiconductor memory comprising:
a first charge pump circuit electrically connected to a first power supply terminal and configured to output a first voltage;
a first resistance, a first end of the first resistance being electrically connected to an output node of the first charge pump circuit;
a second resistance, a first end of the second resistance being electrically connected to a second end of the first resistance;
a first amplifier, a first input end of the first amplifier being electrically connected to the second end of the first resistance and the first end of the second resistance;
a first capacitor, a first end of the first capacitor being electrically connected to the output node of the first charge pump circuit and the first end of the first resistance;
a signal generation circuit, a first node of the signal generation circuit being configured to receive a first signal, the signal generation circuit being configured to generate a second signal;
a first transistor, the first transistor being electrically connected to the first capacitor and the first input end of the first amplifier; and
a second transistor, a control terminal of the second transistor being configured to receive the second signal, the second transistor being electrically connected to the output node in parallel to the first transistor.
2. The non-volatile semiconductor memory according to claim 1 , wherein:
the first resistance includes a third resistance and a fourth resistance, a first end of the third resistance being electrically connected to the output node of the first charge pump circuit, a second end of the third resistance being electrically connected to a first end of the fourth resistance, a second end of the fourth resistance being electrically connected to the first input end of the first amplifier, and
the non-volatile semiconductor memory further comprises:
a second amplifier, a first input end of the second amplifier being electrically connected to the second end of the third resistance and the first end of the fourth resistance.
3. The non-volatile semiconductor memory according to claim 1 , wherein:
an output end of the first amplifier is electrically connected to an input end of the first charge pump circuit.
4. The non-volatile semiconductor memory according to claim 1 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the first amplifier, and an output end of the signal generation circuit is electrically connected to a control terminal of the first transistor.
5. The non-volatile semiconductor memory according to claim 1 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the first amplifier, and an output end of the signal generation circuit is electrically connected to the control terminal of the second transistor.
6. The non-volatile semiconductor memory according to claim 1 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the first amplifier, a first output end of the signal generation circuit is electrically connected to a control terminal of the first transistor, and a second output end of the signal generation circuit is electrically connected to the control terminal of the second transistor.
7. The non-volatile semiconductor memory according to claim 2 , wherein:
an output end of the first amplifier is electrically connected to an input end of the first charge pump circuit.
8. The non-volatile semiconductor memory according to claim 2 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the second amplifier, and an output end of the signal generation circuit is electrically connected to a control terminal of the first transistor.
9. The non-volatile semiconductor memory according to claim 2 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the second amplifier, and an output end of the signal generation circuit is electrically connected to the control terminal of the second transistor.
10. The non-volatile semiconductor memory according to claim 2 , wherein:
an input end of the signal generation circuit is electrically connected to an output end of the second amplifier, a first output end of the signal generation circuit is electrically connected to a control terminal of the first transistor, and a second output end of the signal generation circuit is electrically connected to the control terminal of the second transistor.
11. The non-volatile semiconductor memory according to claim 2 , wherein:
an input end of the first amplifier is electrically connected to an input end of the second amplifier.
12. The non-volatile semiconductor memory according to claim 1 , wherein:
an output end of the signal generation circuit is electrically connected to a control terminal of the first transistor so as to electrically disconnect a first end and a second end of the first transistor at an initial stage of an operation of the first charge pump circuit.
13. The non-volatile semiconductor memory according to claim 1 , wherein:
an output end of the signal generation circuit is electrically connected to the control terminal of the second transistor so as to electrically connect a first end and a second end of the second transistor at an initial stage of an operation of the first charge pump circuit.