Chip-scale package architectures containing a die back side metal and a solder thermal interface material

1. An integrated circuit (IC) package, comprising:

a die having a front side and a backside;

a thermal interface material (TIM) comprising a first metal over the backside, wherein the TIM has a thermal conductivity of not less than 40 W/mK; and

a die backside material (DBM) comprising a second metal over the TIM, wherein the DBM has a CTE of not less than 18×10 −6 m/mK, and wherein an interface between the TIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

2. The IC package of claim 1 , wherein the first metal comprises any one of copper, indium, gallium, aluminum, silver, or tin.

3. The IC package of claim 1 , wherein the second metal comprises any one of copper, zinc, aluminum, or nickel.

4. The IC package of claim 1 , wherein the TIM comprises a plurality of filler particles embedded within the first metal, wherein the filler particles comprise any one of nickel, copper, silver, gold, cobalt, or aluminum.

5. The IC package of claim 1 , wherein the TIM extends a first distance from a first edge and a second edge, and wherein the DBM extends a second distance from a third edge and a fourth edge.

6. The IC package of claim 5 , wherein the TIM extends a third distance between the first edge and the second edge, wherein the third distance is less than the first distance.

7. The IC package of claim 5 , wherein the TIM extends a fourth distance between the third edge and the fourth edge, wherein the fourth distance is less than the second distance.

8. The IC package of claim 5 , wherein the DBM extends the first distance from the first edge to the second edge, and wherein the second metal extends the second distance from the third edge to the fourth edge.

9. The IC package of claim 5 , wherein the DBM extends a fifth distance between the first edge and the second edge, wherein the fifth distance is less than the first distance.

10. The IC package of claim 1 , wherein the DBM has a first z-height and the TIM has a second z-height less than the first z-height, wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.

11. The IC package of claim 1 , wherein the interface comprises any one of a first IMC comprising copper and indium, a second IMC comprising copper, indium, and silver, or a third IMC comprising copper, indium, and tin.

12. The IC package of claim 11 , wherein the interface comprises one layer comprising any of the first IMC, the second IMC, or the third IMC, or the interface comprises at least two layers, wherein each of the at least two layers comprises any one of the first IMC, the second IMC, or the third IMC.

13. The IC package of claim 1 , wherein the die is vertically integrated in a die stack, wherein the die is an uppermost die on the die stack.

14. A system, comprising:

a microprocessor; and

a memory coupled to the microprocessor, the microprocessor or the memory comprising:

an integrated circuit (IC) package, comprising:

a die having a front side and a backside;

a thermal interface material (TIM) comprising a first metal over the backside, wherein the TIM has a thermal conductivity of not less than 40 W/mK; and

a die backside material (DBM) comprising a second metal over the TIM, wherein the DBM has a CTE of not less than 18×10 −6 m/mK, wherein an interface between the TIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

15. The system of claim 14 , wherein the DBM is thermally coupled to a heat sink block, a heat pipe, or a cold plate.