Chip-scale package architectures containing a die back side metal and a solder thermal interface material
An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10 −6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.
1 . An integrated circuit (IC) package structure, comprising:
a die having a front side and a backside;
a first material comprising a first metal over the backside, wherein the first material comprises a plurality of filler particles embedded within the first metal; and
a second material comprising a second metal over the first material, wherein an interface between the first material and the second material comprises at least one intermetallic compound (IMC) of the first metal and the second metal, and wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
2 . The IC package structure of claim 1 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
3 . The IC package structure of claim 1 , wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.
4 . The IC package structure of claim 1 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
5 . The IC package structure of claim 1 , wherein a second interface between the first material and a third material comprises a second IMC.
6 . The IC package structure of claim 1 , wherein the first material has a thermal conductivity of not less than 40 W/mK and wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK.
7 . The IC package structure of claim 1 , further comprising:
a package substrate coupled to the die; and
a board coupled to the package substrate.
8 . An integrated circuit (IC) package structure, comprising:
a die having a front side and a backside;
a first material comprising a first metal over the backside, wherein the first material has a thermal conductivity of not less than 40 W/mK;
a second material comprising a second metal over the first material, wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK; and
a third material over the second material, wherein a first interface between the first material and the second material comprises a first intermetallic compound (IMC) of the first metal and the second metal, and wherein a second interface between the first material and the third material comprises a second IMC.
9 . The IC package structure of claim 8 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
10 . The IC package structure of claim 8 , wherein the first material comprises a plurality of filler particles embedded within the first metal.
11 . The IC package structure of claim 8 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
12 . The IC package structure of claim 8 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height, the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
13 . The IC package structure of claim 8 , further comprising:
a package substrate coupled to the die; and
a board coupled to the package substrate.
14 . An integrated circuit (IC) package structure, comprising:
a die having a front side and a backside;
a first material comprising a first metal over the backside, wherein the first material comprises a plurality of filler particles embedded within the first metal;
a second material comprising a second metal over the first material; and
a third material over the second material, wherein an interface between the first material and the second material comprises a first intermetallic compound (IMC) of the first metal and the second metal, and wherein a second interface between the first material and the third material comprises a second IMC.
15 . The IC package structure of claim 14 , wherein the first metal comprises copper, indium, gallium, aluminum, silver, or tin, or wherein the second metal comprises copper, zinc, aluminum, or nickel.
16 . The IC package structure of claim 14 , wherein the filler particles comprise nickel, copper, silver, gold, cobalt, or aluminum.
17 . The IC package structure of claim 14 , wherein the first material and the second material both cover substantially all of the backside of the die, or the first material is within a recess of the second material.
18 . The IC package structure of claim 14 , wherein the second material has a first z-height and the first material has a second z-height less than the first z-height.
19 . The IC package structure of claim 18 , wherein the first z-height is 500 microns or less, and the second z-height is 150 microns or less.
20 . The IC package structure of claim 14 , wherein the first material has a thermal conductivity of not less than 40 W/mK.
21 . The IC package structure of claim 14 , wherein the second material has a coefficient of thermal expansion (CTE) of not less than 18×10 −6 m/mK.
22 . The IC package structure of claim 14 , further comprising:
a package substrate coupled to the die; and
a board coupled to the package substrate.