Method and apparatus for high speed clock distribution

1. A clock distribution network comprises:

a voltage-to-current driver configured to receive a first voltage signal and output a first current signal;

a transmission line configured to receive the first current signal and output a second current signal;

a current buffer configured to receive the second current signal and output a third current signal;

an LC (inductor-capacitor) tank configured to receive the third current signal and establish a second voltage signal;

a first CDW (capacitively driven wire) configured to receive the second voltage signal and output a third voltage signal;

a first inverter buffer configured to receive the third voltage signal and output a fourth voltage signal;

a second CDW configured to receive the second voltage signal and output a fifth voltage signal; and

a second inverter buffer configured to receive the fifth voltage signal and output a sixth voltage signal.

2. The clock distribution network of claim 1 , wherein the voltage-to-current driver comprises two NMOS (n-channel metal oxide semiconductor) transistors configured as a differential pair of common-source amplifier, or a pseudo differential pair of common-source amplifier.

3. The clock distribution network of claim 1 , wherein the current buffer comprises two NMOS (n-channel metal oxide semiconductor) transistors configured as a differential pair of common-gate amplifier that are cross-coupled via two capacitors.

4. The clock distribution network of claim 1 , wherein the LC tank comprises a parallel connection of an inductor and a capacitor, wherein a center-tap of the inductor connects to a power supply node.

5. The clock distribution network of claim 1 , wherein each of the first CDW and the second CDW comprises a serial connection of a capacitor with a transmission line.

6. A method of clock distribution comprising:

receiving a first voltage signal;

converting the first voltage signal into a first current signal using a voltage-to-current driver;

transmitting the first current signal into a second current signal using a transmission line;

relaying the second current signal into a third current signal using a current buffer;

converting the third current signal into a second voltage signal using an LC (inductor-capacitor) tank as a load;

transmitting the second voltage signal into a third voltage signal using a first CDW (capacitively driven wire);

amplifying the third voltage signal into a fourth voltage signal using a first inverter buffer;

transmitting the second voltage signal into a fifth voltage signal using a second CDW; and

amplifying the fifth voltage signal into a sixth voltage signal using a second inverter buffer.

7. The method of clock distribution of claim 6 , wherein the voltage-to-current driver comprises two NMOS (n-channel metal oxide semiconductor) transistors configured as a differential pair of common-source amplifier or a pseudo differential pair of common-source amplifier.

8. The method of clock distribution of claim 6 , wherein the current buffer comprises two NMOS (n-channel metal oxide semiconductor) transistors configured as a differential pair of common-gate amplifier that are cross-coupled via two capacitors.

9. The method of clock distribution of claim 6 , wherein the LC tank comprises a parallel connection of an inductor and a capacitor, wherein a center-tap of the inductor connects to a power supply node.

10. The method of clock distribution of claim 6 , wherein each of the first CDW and the second CDW comprises a serial connection of a capacitor with a transmission line.

11. A method of clock distribution comprising:

receiving a remote voltage signal;

transmitting the remote voltage signal into a local voltage signal using a current-mode transmission scheme that comprises a cascade of a voltage-to-current driver, a transmission line, a current buffer, and an LC (inductor-capacitor) tank;

transmitting the local voltage signal into a first destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a first capacitively driven wire and a first inverter buffer; and

transmitting the local voltage signal into a second destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a second capacitively driven wire and a second inverter buffer.