Apparatus and method of power efficient high-speed clock transmission

1. A clock transmission circuit comprising:

a voltage-to-current converter configured to convert a first clock into a first current;

a main transmission line configured to convey the first current into a second current;

a transformer comprising a primary inductor and a secondary inductor and configured to convert the second current received via the primary inductor into a second clock output via the secondary inductor;

a tuning capacitor configured to form a resonant network with the secondary inductor; and

a regenerative network connected to the resonant network and configured to provide a negative resistance to enhance resonance of the resonant network.

2. The clock transmission circuit of claim 1 being integrated and fabricated on a substrate using a multi-layer process technology comprising a first metal layer, a second metal layer, and a via layer configured to provide inter-metal-layer connection between the first metal layer and the second metal layer.

3. The clock transmission circuit of claim 1 , wherein the voltage-to-current converter comprises an inverter.

4. The clock transmission circuit of claim 1 , wherein the regenerative network comprises two cross-coupling inverters.

5. The clock transmission circuit of claim 2 , wherein both the primary inductor and the secondary inductor are of spiral topology and a number of turns of the secondary inductor is larger than a number of turns of the primary inductor.

6. The clock transmission circuit of claim 5 , wherein the primary inductor is of single turn and the secondary inductor is of two turns.

7. The clock transmission circuit of claim 5 , wherein the primary inductor and the secondary inductor are laid out in an interleaving topology comprising a combination of metal traces laid out on the first metal layer and the second metal layer.

8. The clock transmission circuit of claim 5 , wherein the primary inductor and the secondary inductor are laid out in a stacked topology comprising a combination of metal traces laid out on the first metal layer and the second metal layer.

9. The clock transmission circuit of claim 5 , further comprising a first capacitively driven wire configured to receive the second clock, either directly or indirectly via a first buffer, and output a third clock, and a first self-biased inverter configured to receive the third clock and output a fourth clock, wherein the first capacitively driven wire comprises a first AC (alternate current) coupling capacitor and a first wire that is a first local transmission line shorter than the main transmission line.

10. The clock transmission circuit of claim 9 , further comprising a second capacitively driven wire configured to receive the second clock, either directly or indirectly via a second buffer, and output a fifth clock, and a second self-biased inverter configured to receive the fifth clock and output a sixth clock, wherein the second capacitively driven wire comprises a second AC coupling capacitor and a second wire that is a second local transmission line shorter than the main transmission line.

11. A method of clock transmission comprising:

converting a first clock into a first current using a voltage-to-current converter;

conveying the first current into a second current using a main transmission line;

using a transformer comprising a primary inductor and a secondary inductor to transform the second current received via the primary inductor into a second clock output via the secondary inductor;

using a tuning capacitor to resonate with the secondary inductor; and

reinforcing the resonance using a regenerative network.

12. The method of clock transmission of claim 11 , further comprising integrating and fabricating the voltage-to-current converter, the main transmission line, the transformer, the tuning capacitor and the regenerative network on a substrate using a multi-layer process technology comprising a first metal layer, a second metal layer, and a via layer configured to provide inter-metal-layer connection between the first metal layer and the second metal layer.

13. The method of clock transmission of claim 11 , wherein the voltage-to-current converter comprises an inverter.

14. The method of clock transmission of claim 11 , wherein the regenerative network comprises two cross-coupling inverters.

15. The method of clock transmission of claim 12 , wherein both the primary inductor and the secondary inductor are of spiral topology and a number of turns of the secondary inductor is larger than a number of turns of the primary inductor.

16. The method of clock transmission of claim 15 , wherein the primary inductor is of single turn and the secondary inductor is of two turns.

17. The method of clock transmission of claim 15 , wherein the primary inductor and the secondary inductor are laid out in an interleaving topology comprising a combination of metal traces laid out on the first metal layer and the second metal layer.

18. The method of clock transmission of claim 15 , wherein the primary inductor and the secondary inductor are laid out in a stacked topology comprising a combination of metal traces laid out on the first metal layer and the second metal layer.

19. The method of clock transmission of claim 15 , further comprising incorporating a first capacitively driven wire configured to receive the second clock, either directly or indirectly via a first buffer, and output a third clock, and a first self-biased inverter configured to receive the third clock and output a fourth clock, wherein the first capacitively driven wire comprises a first AC (alternate current) coupling capacitor and a first wire that is a first local transmission line shorter than the main transmission line.

20. The method of clock transmission of claim 19 , further comprising incorporating a second capacitively driven wire configured to receive the second clock, either directly or indirectly via a second buffer, and output a fifth clock, and a second self-biased inverter configured to receive the fifth clock and output a sixth clock, wherein the second capacitively driven wire comprises a second AC coupling capacitor and a second wire that is a second local transmission line shorter than the main transmission line.