Area efficient traffic generator
A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.
1. A system to monitor the performance of one or more flows on a packet network, said system comprising:
a distributed memory comprising a plurality of programmable instructions and related data;
a processor coupled with said memory to execute one or more of said programmable instructions upon reception of a packet from one of said flow and to modify said related data;
wherein said programmable instructions and related data can be modified without requiring a new load on the system in order to change a behavior.
2. The system of claim 1 in which said processor is implemented as a field programmable gate array (FPGA).
3. A method to monitor the performance at a network device coupled to one or more flows in a packet network, said method comprising:
storing, in a distributed memory, a plurality of programmable instructions and related data;
executing, by a processor coupled to said distributed memory in a system, one or more of said programmable instructions upon reception of a packet from one of said flow and to modify said related data; and
modifying said programmable instructions and related data without requiring a new load on the system in order to change a behavior.
4. The method of claim 3 in which processor is implemented as a field programmable gate array (FPGA).