IP Library Granted Patent US 12,426,367
Granted Patent B2
US 12,426,367 · App. 17/036,619 · Granted Sep 23, 2025

Display device and method of manufacturing display device

Inventors: Jay Bum Kim (Yongin-si, KR); Myeong Ho Kim (Hwaseong-si, KR); Kyoung Seok Son (Seoul, KR); Seung Jun Lee (Suwon-si, KR); Seung Hun Lee (Seoul, KR); Jun Hyung Lim (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H10D86/60H10D86/0223H10D86/421H10D86/481
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,426,367
App. No.
17/036,619
Granted
Sep 23, 2025
Kind
B2
Abstract

A display device includes a substrate, a first active layer on the substrate, a first insulation layer on the first active layer, a first gate electrode on the first insulation layer, the first gate electrode overlapping the first active layer, a second insulation layer on the first gate electrode, a second active layer on the second insulation layer, a first capacitor electrode on the second insulation layer, the first capacitor electrode overlapping the first gate electrode, a third insulation layer on the second active layer and the first capacitor electrode, a second gate electrode on the third insulation layer, the second gate electrode overlapping the second active layer, and a second capacitor electrode on the third insulation layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

Claims (97)

1. A display device, comprising:

a substrate;

a first active layer disposed on the substrate;

a first insulation layer disposed on the first active layer;

a first gate electrode disposed on the first insulation layer, the first gate electrode overlapping the first active layer;

a second insulation layer disposed on the first gate electrode;

a second active layer disposed on the second insulation layer;

a first capacitor electrode disposed on the second insulation layer, the first capacitor electrode overlapping the first gate electrode;

a third insulation layer disposed on the second active layer and the first capacitor electrode;

a second gate electrode disposed on the third insulation layer, the second gate electrode overlapping the second active layer; and

a second capacitor electrode disposed on the third insulation layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

2. The display device of claim 1 , wherein the first capacitor electrode and the second active layer include a same material.

3. The display device of claim 1 , wherein the first active layer includes polycrystalline silicon.

4. The display device of claim 1 , wherein the second insulation layer includes silicon nitride.

5. The display device of claim 1 , wherein a permittivity of the second insulation layer is greater than a permittivity of the third insulation layer.

6. The display device of claim 1 , wherein the second active layer and the first capacitor electrode each include an oxide semiconductor.

7. The display device of claim 1 , wherein the third insulation layer includes silicon oxide.

8. The display device of claim 1 , wherein a hydrogen content of the third insulation layer is less than a hydrogen content of the second insulation layer.

9. The display device of claim 1 , wherein the second capacitor electrode does not overlap the first capacitor electrode.

10. The display device of claim 1 , wherein the second capacitor electrode overlaps the first capacitor electrode.

11. The display device of claim 1 , further comprising:

a fourth insulation layer disposed on the second gate electrode and the second capacitor electrode; and

a connection electrode disposed on the fourth insulation layer, the connection electrode electrically connecting the second capacitor electrode and the first capacitor electrode.

12. The display device of claim 11 , wherein a constant voltage is applied to the connection electrode.

13. The display device of claim 11 , further comprising:

a first source electrode and a first drain electrode disposed on the fourth insulation layer and electrically connected to the first active layer; and

a second source electrode and a second drain electrode disposed on the fourth insulation layer and electrically connected to the second active layer,

wherein the connection electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on a same layer.

14. The display device of claim 13 , further comprising:

a pixel electrode electrically connected to the first source electrode or the first drain electrode;

an emission layer disposed on the pixel electrode; and

an opposite electrode disposed on the emission layer.

15. The display device of claim 1 , further comprising:

a lower electrode disposed between the first insulation layer and the second insulation layer, the lower electrode overlapping the second active layer.

16. The display device of claim 15 , wherein the lower electrode is electrically connected to the second gate electrode.

17. A method of manufacturing a display device, the method comprising:

forming a first active layer on a substrate;

forming a first insulation layer on the first active layer;

forming a first gate electrode on the first insulation layer, the first gate electrode overlapping the first active layer;

forming a second insulation layer on the first gate electrode;

forming a second active layer on the second insulation layer;

forming a first capacitor electrode on the second insulation layer, the first capacitor electrode overlapping the first gate electrode;

forming a third insulation layer on the second active layer and the first capacitor electrode;

forming a second gate electrode on the third insulation layer, the second gate electrode overlapping the second active layer; and

forming a second capacitor electrode on the third insulation layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

18. The method of claim 17 , wherein

the forming of the second active layer and the forming of the first capacitor electrode are simultaneously performed, and

the forming of the second gate electrode and the forming of the second capacitor electrode are simultaneously performed.

19. The method of claim 18 , wherein the forming of the second active layer and the first capacitor electrode comprises:

forming an oxide semiconductor layer on the second insulation layer;

etching the oxide semiconductor layer to form the second active layer and the first capacitor electrode; and

injecting impurities into the second active layer and the first capacitor electrode using the second gate electrode and the second capacitor electrode as masks.

20. The method of claim 18 , wherein the forming of the second gate electrode and the second capacitor electrode comprises:

forming a conductive layer on the third insulation layer; and

etching the conductive layer to form the second gate electrode and the second capacitor electrode.

21. The method of claim 18 , further comprising:

forming a fourth insulation layer on the second gate electrode and the second capacitor electrode;

forming a first contact hole in the third insulation layer and the fourth insulation layer, the first contact hole exposing the first capacitor electrode;

forming a second contact hole in the fourth insulation layer, the second contact hole exposing the second capacitor electrode; and

forming a connection electrode on the fourth insulation layer, the connection electrode filling the first contact hole and the second contact hole.

22. The method of claim 21 , wherein the forming of the first contact hole and the forming of the second contact hole are simultaneously performed.

23. The method of claim 18 , further comprising:

forming a lower electrode between the first insulation layer and the second insulation layer, the lower electrode overlapping the second active layer.

24. The method of claim 23 , wherein the forming of the first gate electrode and the forming of the lower electrode are simultaneously performed.

25. A display device, comprising:

a substrate;

a first transistor including:

a first active layer disposed on the substrate;

a first insulation layer disposed on the first active layer; and

a first gate electrode disposed on the first insulation layer, the first gate electrode overlapping the first active layer;

a capacitor including:

the first gate electrode;

a second insulation layer disposed on the first gate electrode;

a first capacitor electrode disposed on the second insulation layer;

the first capacitor electrode overlapping the first gate electrode;

a third insulation layer disposed on the first capacitor electrode; and

a second capacitor electrode disposed on the third insulation layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode; and

a second transistor including:

a second active layer disposed between the second insulation layer and the third insulation layer, the second active layer and the first capacitor electrode including a same material;

the third insulation layer; and

a second gate electrode disposed on the third insulation layer, the second gate electrode overlapping the second active layer.

26. The display device of claim 25 , wherein the first active layer includes polycrystalline silicon.

27. The display device of claim 25 , wherein the second active layer and the first capacitor electrode each include an oxide semiconductor.

28. The display device of claim 25 , wherein the second transistor further includes a lower electrode disposed between the first insulation layer and the second insulation layer, the lower electrode overlapping the second active layer.

29. The display device of claim 28 , wherein the lower electrode is electrically connected to the second gate electrode.

30. A display device, comprising:

a first active layer on a substrate;

a first gate electrode overlapping the first active layer, the first gate electrode being insulated from the first active layer;

a first capacitor electrode overlapping a first portion of the first gate electrode, the first capacitor electrode being insulated from the first gate electrode;

a second active layer not overlapping the first gate electrode, the second active layer and the first capacitor electrode including a same material;

a second gate electrode overlapping the second active layer, the second gate electrode being insulated from the second active layer; and

a second capacitor electrode overlapping a second portion of the first gate electrode, the second capacitor electrode being insulated from the first gate electrode and electrically connected to the first capacitor electrode.

31. The display device of claim 30 , wherein the second capacitor electrode does not overlap the first capacitor electrode.

32. The display device of claim 30 , wherein the second capacitor electrode overlaps the first capacitor electrode.

33. The display device of claim 30 , further comprising:

a connection electrode overlapping the first capacitor electrode and the second capacitor electrode, the connection electrode electrically connecting the second capacitor electrode and the first capacitor electrode.

34. The display device of claim 30 , wherein the second active layer and the first capacitor electrode are disposed in a same layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2020
From: KIM, JAY BUM; KIM, MYEONG HO; SON, KYOUNG SEOK; LEE, SEUNG JUN; LEE, SEUNG HUN; LIM, JUN HYUNG
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 053921/0259 →
Priority Claims (1)
KR 10-2019-0142684 · Nov 8, 2019 · national
Continuity (1)
Related Publication 20210143189A1 · May 13, 2021
References Cited (24)
US 9165993B2 · Kim · 2015 [cited by examiner]
US 10020354B2 · Kim et al. · 2018 [cited by applicant]
US 10249695B2 · Ono et al. · 2019 [cited by applicant]
US 20040004221A1 · Murade · 2004 [cited by examiner]
US 20120326150A1 · Kim et al. · 2012 [cited by applicant]
US 20130037783A1 · Lee et al. · 2013 [cited by applicant]
US 20180061921A1 · Son et al. · 2018 [cited by applicant]
US 20180145125A1 · Lee et al. · 2018 [cited by applicant]
US 20180277614A1 · Ono · 2018 [cited by examiner]
US 20180366586A1 · Son · 2018 [cited by examiner]
US 20190006521A1 · Noh et al. · 2019 [cited by applicant]
US 20190288048A1 · Kang et al. · 2019 [cited by applicant]
US 20210408190A1 · Yang · 2021 [cited by applicant]
CN 102931209A · 2013 [cited by applicant]
CN 108493198A · 2018 [cited by applicant]
CN 110277427A · 2019 [cited by applicant]
KR 1020070072207 · 2007 [cited by applicant]
KR 1020150081869A · 2015 [cited by applicant]
KR 1020150101418 · 2015 [cited by applicant]
KR 1020180012442 · 2018 [cited by applicant]
KR 1020180025427A · 2018 [cited by applicant]
KR 1020180056497A · 2018 [cited by applicant]
KR 1020190030840A · 2019 [cited by applicant]
Chinese Office Action corresponding to Application No. 202011239736.6, dated on Feb. 27, 2025, 11 pages. [cited by applicant]