Package structure with reinforced element and formation method thereof
A package structure and a formation method of a package structure are provided. The method includes forming multiple conductive vias in a carrier substrate and forming a redistribution structure over the carrier substrate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The method also includes disposing multiple chip structures over the redistribution structure. The method further includes bonding the carrier substrate to a package structure.
1. A method for forming a package structure, comprising:
forming a plurality of conductive structures in a carrier substrate;
forming an interconnection structure over the carrier substrate and the conductive structures, wherein the interconnection structure comprises a passivation layer, a plurality of silicon-containing oxide layers, and a plurality of first conductive features, wherein the passivation layer is thinner than the plurality of silicon-containing oxide layers;
forming a redistribution structure over the interconnection structure, wherein the redistribution structure has a plurality of polymer-containing layers and a plurality of second conductive features, and the redistribution structure is in direct contact with the passivation layer of the interconnection structure;
bonding a plurality of chip structures over the redistribution structure;
forming a protective layer over the redistribution structure to surround the chip structures; and
forming a plurality of conductive connectors over a surface of the carrier substrate, wherein the carrier substrate is between the redistribution structure and the conductive connectors.
2. The method for forming a package structure as claimed in claim 1 , further comprising bonding the conductive connectors to a package substrate.
3. The method for forming a package structure as claimed in claim 1 , further comprising thinning the carrier substrate to expose the conductive structures before the conductive connectors are formed.
4. The method for forming a package structure as claimed in claim 1 , wherein the carrier substrate is made of a semiconductor material.
5. The method for forming a package structure as claimed in claim 4 , further comprising forming a dielectric layer in the carrier substrate before the conductive structures are formed, wherein the dielectric layer electrically isolates the carrier substrate and the conductive structures.
6. The method for forming a package structure as claimed in claim 1 , wherein the carrier substrate is made of a dielectric material.
7. The method for forming a package structure as claimed in claim 1 , further comprising forming at least one deep trench capacitor in the carrier substrate before the redistribution structure is formed.
8. The method for forming a package structure as claimed in claim 1 , further comprising forming a second redistribution structure over the surface of the carrier substrate before the conductive connectors are formed, wherein the carrier substrate is between the redistribution structure and the second redistribution structures.
9. The method for forming a package structure as claimed in claim 8 , wherein the second redistribution structure comprises a plurality of second polymer-containing layers and a plurality of third conductive features.
10. The method for forming a package structure as claimed in claim 1 , further comprising grinding the protective layer to expose at least one of the chip structures while the conductive connectors are attached to a carrier.
11. A method for forming a package structure, comprising:
forming a plurality of conductive vias in a carrier substrate;
forming an interconnection structure over the carrier substrate and the conductive structures, wherein the interconnection structure comprises a passivation layer, a plurality of silicon-containing oxide layers, and a plurality of first conductive features, wherein the passivation layer is thinner than the plurality of silicon-containing oxide layers;
forming a redistribution structure over the carrier substrate, wherein the redistribution structure has a plurality of polymer-containing layers and a plurality of second conductive features, and the redistribution structure is in direct contact with the passivation layer of the interconnection structure;
disposing a plurality of chip structures over the redistribution structure;
bonding the carrier substrate to a package structure; and
forming a thermal conductive structure directly on the chip structures after the chip structures are disposed over the redistribution structure, wherein the thermal conductive structure extends across opposite edges of the chip structures.
12. The method for forming a package structure as claimed in claim 11 , further comprising:
forming a dielectric layer in the carrier substrate;
forming a conductive material over the dielectric layer; and
partially removing the conductive material, wherein remaining portions of the conductive material form the conductive vias.
13. The method for forming a package structure as claimed in claim 12 , further comprising thinning the carrier substrate to expose the conductive vias after the chip structures are disposed and before the carrier substrate is bonded to the package structure.
14. A package structure, comprising:
a reinforced plate;
a plurality of conductive structures penetrating through the reinforced plate;
an interconnection structure over the reinforced plate and the conductive structures, wherein the interconnection structure comprises a passivation layer, a plurality of silicon-containing oxide layers, and a plurality of first conductive features, wherein the passivation layer is thinner than the plurality of silicon-containing oxide layers;
a redistribution structure over the interconnection structure, wherein the redistribution structure comprises a plurality of polymer-containing layers and a plurality of second conductive features, and the redistribution structure is in direct contact with the passivation layer of the interconnection structure;
a plurality of chip structures over the redistribution structure;
a protective layer surrounding the chip structures; and
a plurality of conductive connectors below a bottom surface of the reinforced plate, wherein the reinforced plate is between the redistribution structure and the conductive connectors.
15. The package structure as claimed in claim 14 , wherein the reinforced plate has a first thickness, the redistribution structure has a second thickness, and a ratio of the first thickness to the second thickness is in a range from about 0.5 to about 1.
16. The package structure as claimed in claim 14 , further comprising a second redistribution structure, wherein the second redistribution structure is between the reinforced plate and the conductive connectors, and the second redistribution structure comprises a plurality of second polymer-containing layers and a plurality of third conductive features.
17. The package structure as claimed in claim 14 , further comprising:
a dielectric layer extending along a top surface of the reinforced plate and extending along sidewalls of the conductive structures, wherein the reinforced plate is substantially as wide as the redistribution structure.
18. The package structure as claimed in claim 14 , further comprising at least one deep trench capacitor formed in the reinforced plate.
19. The method for forming a package structure as claimed in claim 11 ,
wherein the interconnection structure is formed before the redistribution structure is formed.
20. The package structure as claimed in claim 14 , wherein the reinforced plate is made of a glass material.