IP Library Granted Patent US 11,264,357
Granted Patent B1
US 11,264,357 · App. 17/075,489 · Granted Mar 1, 2022

Mixed exposure for large die

Inventors: Javier A. Delacruz (San Jose, CA); Belgacem Haba (Saratoga, CA)
Assignee: Invensas Corporation
H01L24/97H01L21/682H01L23/5384H01L23/5389H01L25/0655H01L2225/06541
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Quick Facts
Patent No.
US 11,264,357
App. No.
17/075,489
Granted
Mar 1, 2022
Kind
B1
Abstract

Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

Claims (61)

1. A method comprising:

performing, by a stepper apparatus, a first exposure operation on a first layer of a wafer with respect to a first active region of a first base die defined in the wafer;

moving a reticle of the stepper apparatus over a second active region of a second base die defined in the wafer;

performing, by the stepper apparatus, the first exposure operation on the first layer of the wafer with respect to the second active region of the second base die defined in the wafer; and

performing, by an aligner apparatus, a second exposure operation on the first layer of the wafer with respect to a first inactive region of the first base die defined in the wafer and a second inactive region of the second base die defined in the wafer.

2. The method of claim 1 , further comprising:

prior to the stepper apparatus performing the first exposure operation and the second exposure operation, providing, by the aligner apparatus, a pattern on the wafer for use by the stepper apparatus.

3. The method of claim 1 , further comprising:

performing, by the stepper apparatus, a third exposure operation on a second layer of the wafer with respect to the first active region of the first base die defined in the wafer;

moving the reticle of the stepper apparatus over the second active region of the second base die defined in the wafer;

performing, by the stepper apparatus, the third exposure operation on the second layer of the wafer with respect to the second active region of the second base die defined in the wafer; and

performing, by the aligner apparatus, a fourth exposure operation on the second layer of the wafer with respect to the first inactive region of the first base die defined in the wafer and the second inactive region of the second base die defined in the wafer.

4. The method of claim 3 , wherein:

the stepper apparatus performs the first exposure operation and then the aligner apparatus performs the second exposure operation; and

the stepper apparatus performs the third exposure operation and then the aligner apparatus performs the fourth exposure operation.

5. The method of claim 3 , wherein the stepper apparatus performs the first and third exposure operations prior to the aligner apparatus performing the second and fourth exposure operations.

6. The method of claim 1 , further comprising:

defining, by the aligner apparatus, through silicon vias (TSVs) in the first active region of the first base die;

defining, by the aligner apparatus, through silicon vias (TSVs) in the first inactive region of the first base die;

defining, by the aligner apparatus, through silicon vias (TSVs) in the first active region of the second base die; and

defining, by the aligner apparatus, through silicon vias (TSVs) in the first inactive region of the second base die.

7. The method of claim 6 , wherein at least some of the TSVs are continuous.

8. The method of claim 6 , wherein at least some of the TSVs are disjointed.

9. The method of claim 1 , further comprising:

defining, by the stepper apparatus, through silicon vias (TSVs) in the first active region of the first base die; and

defining, by the stepper apparatus, through silicon vias (TSVs) in the second active region of the second base die.

10. The method of claim 1 , further comprising:

performing, by a direct imaging apparatus, a third exposure operation on a third layer of the wafer with respect to the first inactive region of the first base die defined in the wafer and the second inactive region of the second base die defined in the wafer.

11. The method of claim 1 , wherein the first base die and the second base die comprise interposers.

12. An arrangement comprising:

a stepper apparatus; and

an aligner apparatus,

wherein the arrangement is configured to perform actions comprising:

performing, by the stepper apparatus, a first exposure operation on a first layer of a wafer with respect to a first active region of a first base die defined in the wafer;

moving a reticle of the stepper apparatus over a second active region of a second base die defined in the wafer;

performing, by the stepper apparatus, the first exposure operation on the first layer of the wafer with respect to the second active region of the second base die defined in the wafer; and

performing, by the aligner apparatus, a second exposure operation on the first layer of the wafer with respect to a first inactive region of the first base die defined in the wafer and a second inactive region of the second base die defined in the wafer.

13. The arrangement of claim 12 , wherein the actions further comprise:

prior to the stepper apparatus performing the first exposure operation and the second exposure operation, providing, by the aligner apparatus, a pattern on the wafer for use by the stepper apparatus.

14. The arrangement of claim 12 , wherein the actions further comprise:

performing, by the stepper apparatus, a third exposure operation on a second layer of the wafer with respect to the first active region of the first base die defined in the wafer;

moving the reticle of the stepper apparatus over the second active region of the second base die defined in the wafer;

performing, by the stepper apparatus, the third exposure operation on the second layer of the wafer with respect to the second active region of the second base die defined in the wafer; and

performing, by the aligner apparatus, a fourth exposure operation on the second layer of the wafer with respect to the first inactive region of the first base die defined in the wafer and the second inactive region of the second base die defined in the wafer.

15. The arrangement of claim 14 , wherein:

the stepper apparatus performs the first exposure operation and then the aligner apparatus performs the second exposure operation; and

the stepper apparatus performs the third exposure operation and then the aligner apparatus performs the fourth exposure operation.

16. The arrangement of claim 14 , wherein the stepper apparatus performs the first and third exposure operations prior to the aligner apparatus performing the second and fourth exposure operations.

17. The arrangement of claim 12 , wherein the actions further comprise:

defining, by the aligner apparatus, through silicon vias (TSVs) in the first active region of the first base die;

defining, by the aligner apparatus, through silicon vias (TSVs) in the first inactive region of the first base die;

defining, by the aligner apparatus, through silicon vias (TSVs) in the second active region of the second base die; and

defining, by the aligner apparatus, through silicon vias (TSVs) in the second inactive region of the second base die.

18. The arrangement of claim 17 , wherein at least some of the TSVs are continuous.

19. The arrangement of claim 17 , wherein at least some of the TSVs are disjointed.

20. The arrangement of claim 12 , wherein the actions further comprise:

defining, by the stepper apparatus, through silicon vias (TSVs) in the first active region of the first base die; and

defining, by the stepper apparatus, through silicon vias (TSVs) in the second active region of the second base die.

21. The arrangement of claim 12 , wherein the actions further comprise:

performing, by a direct imaging apparatus, a third exposure operation on a third layer of the wafer with respect to the first inactive region of the first base die defined in the wafer and the second inactive region of the second base die defined in the wafer.

22. The arrangement of claim 12 , wherein the first base die and the second base die comprise interposers.

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073689/0954 →
SECURITY INTEREST Recorded May 3, 2023
From: ADEIA GUIDES INC.; ADEIA IMAGING LLC; ADEIA MEDIA HOLDINGS LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA SOLUTIONS LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 063529/0272 →
CHANGE OF NAME Recorded Aug 30, 2022
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 061357/0485 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2020
From: DELACRUZ, JAVIER A.; HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 054114/0458 →