Memory system, host device and information processing system for error correction processing

1. A memory system comprising:

a nonvolatile memory;

a first decoder configured to execute a first error correction for correcting data read from the nonvolatile memory;

a second decoder configured to execute a second error correction for correcting data read from the nonvolatile memory, an acceptable latency of the second error correction being different from that of the first error correction; and

a controller configured to

receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction,

in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command,

receive a second command issued by the host device, the second command being a command that requests reading data from the non-volatile memory, and

after receiving the first command, output the data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

2. The memory system of claim 1 , wherein

the controller is further configured to execute garbage collection on the nonvolatile memory in response to a third command issued by the host device, the third command being a command that does not request writing data to the nonvolatile memory.

3. The memory system of claim 2 , wherein the controller is further configured to stop the garbage collection when writing data to the nonvolatile memory is required from the host device while the garbage collection is in progress, and to resume the garbage collection after the writing data to the nonvolatile memory is completed.

4. The memory system of claim 1 , wherein:

the nonvolatile memory includes different types of nonvolatile memories; and

the controller is further configured to select a type of nonvolatile memory for writing data from the different types of nonvolatile memories based on a fourth command issued by the host device, the fourth command being a command that requests writing data to the nonvolatile memory and including an attribute of the data to be written.

5. The memory system of claim 4 , wherein the fourth command includes information indicative of update frequency of data to be written to the selected type of the nonvolatile memories.

6. The memory system of claim 4 , wherein:

the different types of nonvolatile memories include a single-level cell (SLC) and a multi-level cell (MLC); and

the controller is further configured to select the SLC from the different types of nonvolatile memories when data to be written to the nonvolatile memory is meta data, and to select the MLC from the different types of nonvolatile memories when data to be written to the nonvolatile memory is user data.

7. A host device configured to control a memory system including a nonvolatile memory, the host device comprising:

a controller configured to:

issue a first command to the memory system, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, and the first command further causing the memory system to select one of a first decoder and a second decoder, the first decoder executing a first error correction for correcting data read from the nonvolatile memory, the second decoder executing a second error correction for correcting data read from the nonvolatile memory, and an acceptable latency of the second error correction being different from that of the first error correction,

issue a second command to the memory system, the second command being a command that requests reading data from the nonvolatile memory, and the first command causing the memory system to output the data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

8. The host device of claim 7 , wherein the controller is further configured to issue a third command to the memory system for causing the memory system to execute garbage collection on the nonvolatile memory, the third command being a command that does not request writing data to the memory system.

9. The host device of claim 8 , wherein the controller is further configured to cause the memory system to stop the garbage collection when writing data to the memory system while the garbage collection is in progress in the memory system, and to cause the memory system to resume the garbage collection after the writing data to the memory system is completed.

10. The host device of claim 7 , wherein:

the nonvolatile memory includes different types of nonvolatile memories; and

the controller is further configured to issue a fourth command to the memory system, the fourth command being a command that requests writing data to the memory system, including an attribute of the data to be written, and causing the memory system to select a type of nonvolatile memory for writing data from the different types of nonvolatile memories.

11. The host device of claim 10 , wherein the fourth command includes information indicative of update frequency of data to be written to the selected type of nonvolatile memory.

12. The host device of claim 10 , wherein:

the different types of nonvolatile memories include a single-level cell (SLC) and a multi-level cell (MLC); and

the controller is further configured to cause the memory system to select the SLC from the different types of nonvolatile memories when data to be written the memory system is meta data, and to cause the memory system to select the MLC from the different types of nonvolatile memories when data to be written to the memory system is user data.

13. The host device of claim 7 , wherein the controller is further configured to control a plurality of memory systems including the memory system, and to read data from another memory system in the plurality of memory systems when an error occurs upon reading data from the memory system.

14. An information processing system comprising:

a memory system including:

a nonvolatile memory;

a first decoder configured to execute a first error correction for correcting data read from the nonvolatile memory; and

a second decoder configured to execute a second error correction for correcting read data from the nonvolatile memory, an acceptable latency of the second error correction being different from that of the first error correction; and

a host device configured to control the memory system, wherein:

the host device is configured to issue a first command and a second command to the memory system, the first command being a command that requests neither reading or writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, the second command being a command that requests reading data from the memory system; and wherein:

the memory system is configured to:

receive the first command from the host device,

in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command,

receive the second command from the host device after receiving the first command, and

after receiving the first command, output the data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

15. The information processing system of claim 14 , wherein:

the host device is further configured to issue a third command to the memory system, the third command being a command that does not request writing data to the memory system; and

the memory system is further configured to execute garbage collection on the nonvolatile memory in response to the third command.

16. The information processing system of claim 15 , wherein the host device is further configured to cause the memory system to stop the garbage collection when writing data to the memory system while the garbage collection is in progress in the memory system, and to cause the memory system to resume the garbage collection after the writing data to the memory system is completed.

17. The information processing system of claim 14 , wherein:

the nonvolatile memory includes different types of nonvolatile memories;

the host device is further configured to issue a fourth command to the memory system, the fourth command being a command that requests writing data to the memory system and including an attribute of the data to be written; and

the memory system is configured to select a type of nonvolatile memory for writing data from the different types of nonvolatile memories based on the received fourth command.

18. The information processing system of claim 17 , wherein the fourth command includes information indicative of update frequency of data to be written to the selected type of nonvolatile memory.

19. The information processing system of claim 17 , wherein:

the different types of nonvolatile memories include a single-level cell (SLC) and a multi-level cell (MLC); and

the host device is further configured to cause the memory system to select the SLC from the different types of nonvolatile memories when data to be written to the memory system is meta data, and to cause the memory system to select the MLC from the different types of nonvolatile memories when data to be written to the memory system is user data.

20. The information processing system of claim 14 , wherein the host device is further configured to control a plurality of memory systems including the memory system, and to read data from another memory system in the plurality of memory systems when an error occurs upon reading data from the memory system.