Semiconductor structure with isolating feature and method for forming the same
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a fin structure protruding from the substrate. The semiconductor structure also includes nanostructures formed over the fin structure and a gate structure surrounding the nanostructures. The semiconductor structure also includes a source/drain structure connected to the nanostructures and an isolating feature sandwiched between the fin structure and the source/drain structure.
1. A semiconductor structure, comprising:
a substrate;
a fin structure protruding from the substrate;
nanostructures formed over the fin structure;
inner spacers vertically sandwiched between the nanostructures;
a gate structure surrounding the nanostructures;
a source/drain structure connected to the nanostructures; and
an isolating feature sandwiched between the fin structure and the source/drain structure,
wherein a portion of the inner spacers is laterally sandwiched between the isolating feature and the gate structure.
2. The semiconductor structure as claimed in claim 1 , wherein a top surface of the isolating feature is lower than a bottommost surface of the nanostructures.
3. The semiconductor structure as claimed in claim 1 , wherein a top surface of the isolating feature is higher than a bottommost surface of the nanostructures.
4. The semiconductor structure as claimed in claim 1 , wherein the isolating feature is made of an undoped semiconductor material.
5. The semiconductor structure as claimed in claim 1 , wherein the isolating feature is made of an insulating material.
6. The semiconductor structure as claimed in claim 1 , wherein the isolating feature has a curved top surface.
7. The semiconductor structure as claimed in claim 1 , wherein the isolating feature comprises a liner in direct contact with the fin structure and an insulating material layer over the liner and in direct contact with the source/drain structure.
8. The semiconductor structure as claimed in claim 1 , further comprising:
a gate spacer formed on a sidewall of the gate structure, wherein the gate spacer vertically overlaps the inner spacers.
9. The semiconductor structure as claimed in claim 1 , wherein a top surface of the isolating feature is higher than a bottom surface of the inner spacers.
10. A semiconductor structure, comprising:
a substrate;
a first fin structure protruding from the substrate;
first nanostructures formed over the first fin structure;
a gate structure wrapping around the first nanostructures at a channel region;
an isolating feature covering a top surface of the first fin structure at a source/drain region; and
a first source/drain structure formed over the isolating feature and connected to the first nanostructures,
wherein the isolating feature is separated from the first nanostructures by the first source/drain structure.
11. The semiconductor structure as claimed in claim 10 , further comprising:
first inner spacers formed between the first nanostructures,
wherein the isolating feature and the gate structure are separated by the first inner spacers.
12. The semiconductor structure as claimed in claim 10 , further comprising:
an isolation structure formed around the first fin structure, wherein a bottom surface of the isolating feature is lower than a top surface of the isolation structure.
13. The semiconductor structure as claimed in claim 10 , wherein the isolating feature is spaced apart from the gate structure.
14. A method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers over a substrate;
patterning the first semiconductor material layers, the second semiconductor material layers, and the substrate to form a fin structure;
forming spacers at opposite sides of the fin structure;
forming a source/drain recess in a source/drain region of the fin structure between the spacers;
forming an isolating feature in the source/drain recess between the spacers;
forming a source/drain structure covering the isolating feature;
removing the first semiconductor material layers to form nanostructures from the second semiconductor material layers in a channel region; and
forming a gate structure wrapping around the nanostructures.
15. The method for manufacturing the semiconductor structure as claimed in claim 14 , wherein a middle portion of the isolating feature is higher than an edge portion of the isolating feature.
16. The method for manufacturing the semiconductor structure as claimed in claim 14 , wherein a middle portion of the isolating feature is lower than an edge portion of the isolating feature.
17. The method for manufacturing the semiconductor structure as claimed in claim 14 , further comprising:
removing the first semiconductor material layers and the second semiconductor material layers at the source/drain region to form the source/drain recess,
wherein the isolating feature is formed in a bottom portion of the source/drain recess.
18. The method for manufacturing the semiconductor structure as claimed in claim 14 , wherein the isolating feature is made of an undoped Si or undoped SiGe.
19. The method for manufacturing the semiconductor structure as claimed in claim 14 , wherein the isolating feature comprises multiple dielectric layers.
20. The method for manufacturing the semiconductor structure as claimed in claim 14 , further comprising:
forming an isolation structure around the fin structure,
wherein a top portion of the isolating feature is higher than a top surface of the isolating feature, and a bottom portion of the isolating feature is lower than a bottom surface of the isolation structure.