IP Library Granted Patent US 11,519,943
Granted Patent B2
US 11,519,943 · App. 17/089,842 · Granted Dec 6, 2022

Multi wire bonding with current sensing method

Inventors: Hiroshi Inoguchi (Tatebayashi, JP); Takashi Nagashima (Sano, JP); Masaru Maeda (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G01R19/0092H01L22/14H01L23/49575H01L24/45H01L24/48H01L24/49H01L24/85H01L25/16H01L2224/45124H01L2224/45144H01L2224/48245H01L2224/49112H01L2224/49505
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Quick Facts
Patent No.
US 11,519,943
App. No.
17/089,842
Granted
Dec 6, 2022
Kind
B2
Abstract

Implementations of a semiconductor package system may include a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground; and a second bond wire bonded to the portion of the leadframe and to a control integrated circuit. The portion of the leadframe may form a current sense area and the control integrated circuit may be configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

Claims (30)

1. A semiconductor package system comprising:

a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground;

a second bond wire bonded to the portion of the leadframe and to a control integrated circuit; and

a third bond wire bonded to the portion of the leadframe and to the pad;

wherein the portion of the leadframe forms a current sense area; and

wherein the control integrated circuit is configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

2. The system of claim 1 , wherein the semiconductor die is an insulated gate bipolar transistor.

3. The system of claim 1 , wherein the first bond wire comprises aluminum.

4. The system of claim 1 , wherein the first bond wire is bonded at three locations.

5. The system of claim 1 , wherein the third bond wire comprises aluminum.

6. The system of claim 1 , wherein a junction temperature between the pad and the first bond wire and the third bond wire is reduced by dividing the total current with the first bond wire and the third bond wire.

7. A semiconductor package system comprising:

a first bond wire bonded to a portion of a substrate and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground;

a second bond wire bonded to the portion of the substrate and configured to be bonded to a control integrated circuit; and

a third bond wire bonded to the portion of the substrate and to the pad;

wherein the portion of the substrate forms a current sense area configured to allow the control integrated circuit to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

8. The system of claim 7 , wherein the semiconductor die is an insulated gate bipolar transistor.

9. The system of claim 7 , wherein the first bond wire comprises aluminum.

10. The system of claim 7 , wherein the first bond wire is bonded at three locations.

11. The system of claim 7 , wherein the third bond wire comprises aluminum.

12. The system of claim 7 , wherein a junction temperature between the pad and the first bond wire and the third bond wire is reduced by dividing the total current with the first bond wire and the third bond wire.

13. A method of current sensing in a semiconductor package, the method comprising:

bonding a first bond wire to a portion of one of a substrate or a leadframe, to a pad of a semiconductor die and to one of a power source or a ground;

bonding a second bond wire to the portion of the one of the substrate or the leadframe and to a control integrated circuit;

bonding a third bond wire to the portion of one of the substrate or the leadframe and to the pad; and

measuring a current flowing through the first bond wire using the control integrated circuit, the second bond wire, and the portion of one of the substrate or the leadframe.

14. The method of claim 13 , wherein the semiconductor die is an insulated gate bipolar transistor.

15. The method of claim 13 , wherein the first bond wire and the third bond wire comprises aluminum.

16. The method of claim 13 , wherein the second bond wire comprises gold.

17. The method of claim 13 , further comprising reducing a junction temperature between the pad and the first bond wire and the third bond wire by dividing the total current between the first bond wire and the third bond wire.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2020
From: INOGUCHI, HIROSHI; NAGASHIMA, TAKASHI; MAEDA, MASARU
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054283/0261 →