Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

1. A nanowire transistor, comprising:

a nanowire disposed on a substrate, the nanowire having an undoped channel region of a first semiconductor material disposed longitudinally between and electrically coupled with an undoped semiconductor source region and an undoped semiconductor drain region;

a gate stack having a gate conductor and a gate insulator wrapped around the undoped channel region of the nanowire;

wherein the undoped semiconductor source region is included in a source stack having a source conductor and an interfacial layer coaxially wrapped around the semiconductor source region, and the undoped semiconductor drain region is included in a drain stack having a drain conductor and an interfacial layer coaxially wrapped around the semiconductor drain region.

2. The nanowire transistor of claim 1 , wherein the source conductor is separated from the gate conductor by an insulating material layer.

3. The nanowire transistor of claim 1 , wherein the source conductor is separated from the gate conductor by a gap.

4. The nanowire transistor of claim 1 , wherein the drain conductor is separated from the gate conductor by an insulating material layer.

5. The nanowire transistor of claim 1 , wherein the drain conductor is separated from the gate conductor by a gap.

6. The nanowire transistor of claim 1 , wherein a Schottky barrier between the source conductor and the semiconductor source region has a negative Schottky barrier height.

7. The nanowire transistor of claim 1 , wherein a Schottky barrier between the source conductor and the semiconductor source region is between −0.1 eV and −0.5 eV.

8. The nanowire transistor of claim 1 , wherein the interfacial layer of the source stack comprises a material that would be an insulator in its bulk state.

9. The nanowire transistor of claim 1 , wherein the interfacial layer of the source stack comprises a material that would be a semiconductor in its bulk state.

10. The nanowire transistor of claim 1 , wherein the interfacial layer of the drain stack comprises a material that would be an insulator in its bulk state.

11. The nanowire transistor of claim 1 , wherein the interfacial layer of the drain stack comprises a material that would be a semiconductor in its bulk state.

12. The nanowire transistor of claim 1 , wherein the interfacial layer of the source stack is a monolayer of a Group V element.

13. The nanowire transistor of claim 1 , wherein the interfacial layer of the source stack is a monolayer of a Group VI element.

14. The nanowire transistor of claim 1 , wherein the interfacial layer of the source stack is a monolayer of a Group III element.

15. The nanowire transistor of claim 1 , wherein the interfacial layer of the drain stack is a monolayer of a Group V element.

16. The nanowire transistor of claim 1 , wherein the interfacial layer of the drain stack is a monolayer of a Group VI element.

17. The nanowire transistor of claim 1 , wherein the interfacial layer of the drain stack is a monolayer of a Group III element.

18. The nanowire transistor of claim 1 , wherein the undoped channel region, the undoped semiconductor source region, and the undoped semiconductor drain region are all comprised of the first semiconductor material.

19. The nanowire transistor of claim 17 , wherein the first semiconductor material is one of: silicon, germanium, silicon carbide, a compound semiconductor, a fullerene, or an alloy comprising two or more of silicon, germanium, carbon and tin.

20. The nanowire transistor of claim 1 , wherein the undoped semiconductor source region and the undoped semiconductor drain region are not comprised of the first semiconductor material.

21. The nanowire transistor of claim 1 , wherein the source conductor comprises a degenerately doped n-type semiconductor.